clock domain switch fast to slow

Discussion in 'VHDL' started by axr0284, Jan 22, 2007.

  1. axr0284

    axr0284 Guest

    Hi,
    I need to send a pulse for a clock domain running at 62.5 MHZ to
    another domain running at 45 MHz.

    I implemented the pulse synchronizer circuit which consists of a mux
    with 4 FF and an XOR at the end.
    I got that from an article by Mike Stein that I read:
    Crossing the abyss: asynchronous signals in a synchronous world.

    The problem is that the pulse only takes 16 ns in the fast domain which
    is less than 1 period of the clock in the second domain so the circuit
    does not detect it. If I used two clock cycle then it works but it kind
    of defeats the purpose of the circuit in that "it is to take a single
    clockwide pulse from one clock domain and create a single clockwide
    pulse in a new domain"

    I would appreciate any thoughts on that.
    Amish
    axr0284, Jan 22, 2007
    #1
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  2. axr0284 wrote:

    > Hi,
    > I need to send a pulse for a clock domain running at 62.5 MHZ to
    > another domain running at 45 MHz.
    >
    > I implemented the pulse synchronizer circuit which consists of a mux
    > with 4 FF and an XOR at the end.
    > I got that from an article by Mike Stein that I read:
    > Crossing the abyss: asynchronous signals in a synchronous world.
    >
    > The problem is that the pulse only takes 16 ns in the fast domain
    > which is less than 1 period of the clock in the second domain so the
    > circuit does not detect it. If I used two clock cycle then it works
    > but it kind of defeats the purpose of the circuit in that "it is to
    > take a single clockwide pulse from one clock domain and create a
    > single clockwide pulse in a new domain"


    Basically, no matter what you implement to do this, you'll have
    essentially reinvented a 0-bit, 1-entry asynchronous FIFO.

    If you don't know how to implement that yourself, contact me via e-mail
    and I'd be happy to give you a quick tutorial on asynchronous
    clock-to-clock crossings or send you some GPL'd VHDL code that does
    exactly what you're asking.

    --
    Wesley J. Landaker <> <xmpp:>
    OpenPGP FP: 4135 2A3B 4726 ACC5 9094 0097 F0A9 8A4C 4CD6 E3D2
    Wesley J. Landaker, Jan 22, 2007
    #2
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  3. axr0284

    Dal Guest

    Have the input pulse toggle a signal in the source clock domain.
    Resync this signal to the destination clock domain. Do an edge detect
    on the resync'ed signal.

    Note the limitation that your source pulse rate must be less frequent
    than your maximum resync delay.

    Welcome to the synchronous world.

    axr0284 wrote:
    > Hi,
    > I need to send a pulse for a clock domain running at 62.5 MHZ to
    > another domain running at 45 MHz.
    >
    > I implemented the pulse synchronizer circuit which consists of a mux
    > with 4 FF and an XOR at the end.
    > I got that from an article by Mike Stein that I read:
    > Crossing the abyss: asynchronous signals in a synchronous world.
    >
    > The problem is that the pulse only takes 16 ns in the fast domain which
    > is less than 1 period of the clock in the second domain so the circuit
    > does not detect it. If I used two clock cycle then it works but it kind
    > of defeats the purpose of the circuit in that "it is to take a single
    > clockwide pulse from one clock domain and create a single clockwide
    > pulse in a new domain"
    >
    > I would appreciate any thoughts on that.
    > Amish
    Dal, Jan 23, 2007
    #3
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