Clock edge during unstable input

Discussion in 'VHDL' started by Jerker Hammarberg \(DST\), Oct 1, 2003.

  1. Hello! I've been looking at the RTL schematic results of some synthesis and
    realize that inputs aren't really synchronized with the clock, although the
    process as such is completely synchronized (that is, everything takes place
    inside a "if clk'event and clk = '1' then"). I am worried about what might
    happen if an input is changing right at the moment of a clock rising edge -
    is it possible that some receivers of the input signal will assume the new
    value, while others will assume the old value?

    Here is an example where the problem could arise:

    Inputs:
    * zeroes: std_logic_vector(1023 downto 0) -- always '0'
    * ones: std_logic_vector(1023 downto 0) -- always '1'
    * switch_signal: std_logic -- switches between '0' and '1'
    Outputs:
    * error: std_logic -- will signal this problem
    Internal signals:
    * buffer: std_logic_vector(1023 downto 0)

    process(clk)
    begin
    if clk'event and clk = '1' then
    if switch_signal = '1' then
    buffer <= ones;
    else
    buffer <= zeroes;
    end if;
    end if;
    error <= buffer(1023) xor buffer(0);
    end process;

    If zeroes is always an array of '0' and ones is always an array of '1'
    during a simulation, then it would be impossible to get the error,
    regardless of how I switch the switch_signal. But in reality, say that the
    switch_signal net is changing from '0' to '1' and is not yet stable when a
    positive clock edge occurs. Then some of the muxes feeding zeroes/ones to
    buffer will still feed zeroes, while others will feed ones, so there may be
    both zeroes and ones clocked into the buffer, and the error will occur.

    Is this right, and if so, what can I do about it? Do I need to clock
    switch_signal into an internal signal to get rid of the problem?

    Finally, a more general question: This is an example of a problem that will
    not be revealed in verification. Are there other such problems? Does anyone
    know of a good book or a tutorial about all these things one should know
    about?

    /Jerker
    Jerker Hammarberg \(DST\), Oct 1, 2003
    #1
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  2. "Jerker Hammarberg (DST)" <> wrote in message
    news:3f7ac7f0$...
    > Hello! I've been looking at the RTL schematic results of some synthesis

    and
    > realize that inputs aren't really synchronized with the clock, although

    the
    > process as such is completely synchronized (that is, everything takes

    place
    > inside a "if clk'event and clk = '1' then"). I am worried about what might
    > happen if an input is changing right at the moment of a clock rising

    edge -
    > is it possible that some receivers of the input signal will assume the new
    > value, while others will assume the old value?
    >
    > Here is an example where the problem could arise:
    >
    > Inputs:
    > * zeroes: std_logic_vector(1023 downto 0) -- always '0'
    > * ones: std_logic_vector(1023 downto 0) -- always '1'
    > * switch_signal: std_logic -- switches between '0' and '1'
    > Outputs:
    > * error: std_logic -- will signal this problem
    > Internal signals:
    > * buffer: std_logic_vector(1023 downto 0)
    >
    > process(clk)
    > begin
    > if clk'event and clk = '1' then
    > if switch_signal = '1' then
    > buffer <= ones;
    > else
    > buffer <= zeroes;
    > end if;
    > end if;
    > error <= buffer(1023) xor buffer(0);
    > end process;
    >
    > If zeroes is always an array of '0' and ones is always an array of '1'
    > during a simulation, then it would be impossible to get the error,
    > regardless of how I switch the switch_signal. But in reality, say that the
    > switch_signal net is changing from '0' to '1' and is not yet stable when a
    > positive clock edge occurs. Then some of the muxes feeding zeroes/ones to
    > buffer will still feed zeroes, while others will feed ones, so there may

    be
    > both zeroes and ones clocked into the buffer, and the error will occur.
    >
    > Is this right, and if so, what can I do about it? Do I need to clock
    > switch_signal into an internal signal to get rid of the problem?


    In real hardware you would indeed synchronize your asynchronous input signal
    using an extra FF for switch_signal the way you describe above. Maybe you
    even add two FFs in serie to reduce metastability.

    Egbert Molenkamp
    Egbert Molenkamp, Oct 1, 2003
    #2
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  3. Jerker Hammarberg \(DST\)

    Jim Wu Guest

    > Is this right, and if so, what can I do about it? Do I need to clock
    > switch_signal into an internal signal to get rid of the problem?


    Yes, you will need to synchronize switch_signal if it is asynchrous to the
    clock. Normally people use two-stage FFs as the synchronizer. It will not
    get rid of the problem completely, but will decrease the probability of
    getting into metastability state.


    Jim Wu
    (remove capital letters)
    http://www.geocities.com/jimwu88/chips
    Jim Wu, Oct 2, 2003
    #3
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