Clock Frequency & timming constraints

Discussion in 'VHDL' started by samehsh, Nov 22, 2008.

  1. samehsh

    samehsh

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    Jun 8, 2008
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    Tool: Xilinx ISE 9.1

    I'm doing a multiplier for binary number and i get a clock frequecncy value in synthesis report does this meaning thing? specially i assign other clock frequency in timing constraints.
    samehsh, Nov 22, 2008
    #1
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  2. samehsh

    jeppe

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    I guess the value you got in the rapport would be the Max frequency - you can use lower frequencies in the real design

    Jeppe
    jeppe, Nov 22, 2008
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