clock frequency

Discussion in 'VHDL' started by Amit, Apr 16, 2008.

  1. Amit

    Amit Guest

    Hello,

    I'm using dcfifo (Altera) and rdclk should be clocked using a signal
    as bclk = 18.432 Mhz. I always have worked with integer values but no
    idea how to generate such a clock. Any hint will be appreciated.

    Thanks.
     
    Amit, Apr 16, 2008
    #1
    1. Advertising

  2. Amit wrote:

    > I'm using dcfifo (Altera) and rdclk should be clocked using a signal
    > as bclk = 18.432 Mhz. I always have worked with integer values but no
    > idea how to generate such a clock.


    I would buy one and solder it on the board.
    http://www.google.com/search?q=18.432 Mhz oscillator


    -- Mike Treseler
     
    Mike Treseler, Apr 16, 2008
    #2
    1. Advertising

  3. Amit

    Amit Guest

    On Apr 16, 10:51 am, Mike Treseler <> wrote:
    > Amit wrote:
    > > I'm using dcfifo (Altera) and rdclk should be clocked using a signal
    > > as bclk = 18.432 Mhz. I always have worked with integer values but no
    > > idea how to generate such a clock.

    >
    > I would buy one and solder it on the board.http://www.google.com/search?q=18.432 Mhz oscillator
    >
    >         -- Mike Treseler



    What I need is generating a clock frequency for 1.536Mhz. I typed a
    wrong number before. This will clock the rdclk in dcfifo.
     
    Amit, Apr 16, 2008
    #3
  4. Amit

    Guest

    On Apr 16, 2:51 pm, Amit <> wrote:
    > On Apr 16, 10:51 am, Mike Treseler <> wrote:
    >
    > > Amit wrote:
    > > > I'm using dcfifo (Altera) and rdclk should be clocked using a signal
    > > > as bclk = 18.432 Mhz. I always have worked with integer values but no
    > > > idea how to generate such a clock.

    >
    > > I would buy one and solder it on the board.http://www.google.com/search?q=18.432 Mhz oscillator

    >
    > > -- Mike Treseler

    >
    > What I need is generating a clock frequency for 1.536Mhz. I typed a
    > wrong number before. This will clock the rdclk in dcfifo.


    Umm, I have a hunch, that what Mike was trying to say, was "be more
    specific".

    If that's all you need and you can do it, just buy the can.
    Otherwise, if you need to create this from existing clocks in your
    system, you need to tell us (1) what clocks you have, (2) what
    technology resources you might have available in your FPGA, and (3)
    what the constraints on this clock are. By constraints, I mean, does
    it have to be synchronized to some other clock to avoid slow data
    leaks or overflows? Or could it be 1.5355 and no one would be any the
    wiser?

    Your two basic choices are probably to use one of the FPGA resources
    (DPLL,DCM) as a clock synthesizer, using a multiply-by-N/divide-by-M
    configuration, or (since the freq is so low), using a direct digital
    synthesizer (google this, or DDS).

    Or is this a simulation/testbench question?

    And, being a little pedantic, what's not integer about 18432000
    Hz :)

    - Kenn
     
    , Apr 17, 2008
    #4
  5. Amit

    Amit Guest

    On Apr 16, 6:53 pm, wrote:
    > On Apr 16, 2:51 pm, Amit <> wrote:
    >
    > > On Apr 16, 10:51 am, Mike Treseler <> wrote:

    >
    > > > Amit wrote:
    > > > > I'm using dcfifo (Altera) and rdclk should be clocked using a signal
    > > > > as bclk = 18.432 Mhz. I always have worked with integer values but no
    > > > > idea how to generate such a clock.

    >
    > > > I would buy one and solder it on the board.http://www.google.com/search?q=18.432 Mhz oscillator

    >
    > > >         -- Mike Treseler

    >
    > > What I need is generating a clock frequency for 1.536Mhz. I typed a
    > > wrong number before. This will clock the rdclk in dcfifo.

    >
    > Umm, I have a hunch, that what Mike was trying to say, was "be more
    > specific".
    >
    > If that's all you need and you can do it, just buy the can.
    > Otherwise, if you need to create this from existing clocks in your
    > system, you need to tell us (1) what clocks you have, (2) what
    > technology resources you might have available in your FPGA, and (3)
    > what the constraints on this clock are. By constraints, I mean, does
    > it have to be synchronized to some other clock to avoid slow data
    > leaks or overflows? Or could it be 1.5355 and no one would be any the
    > wiser?
    >
    > Your two basic choices are probably to use one of the FPGA resources
    > (DPLL,DCM) as a clock synthesizer, using a multiply-by-N/divide-by-M
    > configuration, or (since the freq is so low), using a direct digital
    > synthesizer (google this, or DDS).
    >
    > Or is this a simulation/testbench question?
    >
    > And, being a little pedantic, what's not integer about 18432000
    > Hz  :)
    >
    >  - Kenn



    Hi Kenn,

    I truly appreciate your help and time you spent to expalin it. Ok,
    I'll go with more details:

    I'm planning to make a FIFO using (Quratus II and Altera MegaFunction
    dcfifo) on DE2 board. Goal is palying music from a SD card or any
    other storage unit. One of the steps is using a dcfifo is embedded
    into the entity which I called it fifo.

    As you know better, the main clock is 50Mhz which is what DE2 is
    giving me but I need to have two other internal clocks (to drive the
    read_clock signal and also drive a shift-register ).

    These two clocks are clk0 and clk1.

    clk0 which should be 18.432Mhz then base on this clock I need to have
    clk1 which its frequency is 1.536Mhz.

    Question: What is the proper method? do I have to write code to create
    a clock with 18.432Mhz frequency? or only I can define a signal and
    set it as clock in Waveform?

    I did search for "vhdl+clock+custom" or ... but didn't find anything
    helpful if you know please pass it to me.

    I understand these questions are easy for members of this group and I
    try not to post them as much as possible but sometimes I cannot find
    everyting in books.

    Once again thank you.
     
    Amit, Apr 17, 2008
    #5
  6. Amit

    Guest

    On Apr 16, 11:38 pm, Amit <> wrote:
    > On Apr 16, 6:53 pm, wrote:
    >
    >
    >
    > > On Apr 16, 2:51 pm, Amit <> wrote:

    >
    > > > On Apr 16, 10:51 am, Mike Treseler <> wrote:

    >
    > > > > Amit wrote:
    > > > > > I'm using dcfifo (Altera) and rdclk should be clocked using a signal
    > > > > > as bclk = 18.432 Mhz. I always have worked with integer values but no
    > > > > > idea how to generate such a clock.

    >
    > > > > I would buy one and solder it on the board.http://www.google.com/search?q=18.432 Mhz oscillator

    >
    > > > > -- Mike Treseler

    >
    > > > What I need is generating a clock frequency for 1.536Mhz. I typed a
    > > > wrong number before. This will clock the rdclk in dcfifo.

    >
    > > Umm, I have a hunch, that what Mike was trying to say, was "be more
    > > specific".

    >
    > > If that's all you need and you can do it, just buy the can.
    > > Otherwise, if you need to create this from existing clocks in your
    > > system, you need to tell us (1) what clocks you have, (2) what
    > > technology resources you might have available in your FPGA, and (3)
    > > what the constraints on this clock are. By constraints, I mean, does
    > > it have to be synchronized to some other clock to avoid slow data
    > > leaks or overflows? Or could it be 1.5355 and no one would be any the
    > > wiser?

    >
    > > Your two basic choices are probably to use one of the FPGA resources
    > > (DPLL,DCM) as a clock synthesizer, using a multiply-by-N/divide-by-M
    > > configuration, or (since the freq is so low), using a direct digital
    > > synthesizer (google this, or DDS).

    >
    > > Or is this a simulation/testbench question?

    >
    > > And, being a little pedantic, what's not integer about 18432000
    > > Hz :)

    >
    > > - Kenn

    >
    > Hi Kenn,
    >
    > I truly appreciate your help and time you spent to expalin it. Ok,
    > I'll go with more details:
    >
    > I'm planning to make a FIFO using (Quratus II and Altera MegaFunction
    > dcfifo) on DE2 board. Goal is palying music from a SD card or any
    > other storage unit. One of the steps is using a dcfifo is embedded
    > into the entity which I called it fifo.
    >
    > As you know better, the main clock is 50Mhz which is what DE2 is
    > giving me but I need to have two other internal clocks (to drive the
    > read_clock signal and also drive a shift-register ).
    >
    > These two clocks are clk0 and clk1.
    >
    > clk0 which should be 18.432Mhz then base on this clock I need to have
    > clk1 which its frequency is 1.536Mhz.
    >
    > Question: What is the proper method? do I have to write code to create
    > a clock with 18.432Mhz frequency? or only I can define a signal and
    > set it as clock in Waveform?
    >
    > I did search for "vhdl+clock+custom" or ... but didn't find anything
    > helpful if you know please pass it to me.
    >
    > I understand these questions are easy for members of this group and I
    > try not to post them as much as possible but sometimes I cannot find
    > everyting in books.
    >
    > Once again thank you.


    It can be kind of hard to just jump in and understand how to do all
    these things if you have no background in hardware. A common mistake
    that software people make is that VHDL is somehow "just another
    language". The reality is that, in order to design hardware, you
    really ought to understand what you want to build *first*, and have
    the idea of the building blocks, registers, overall data flow, etc
    mapped out in your head (if not on paper). Then, the task of
    implementing it is just mechanical work. But if you don't understand
    hardware to begin with, you're going to have a rough time. I'd really
    advise you to find a good college-level digital design textbook and
    work through it from front to back. Also, read as many application
    notes (Xilinx or Altera) as you can handle and try to understand how
    the problems are being solved in hardware, at a circuit level. Then
    you'll start to see how to achieve what you need, and can move on to
    the mechanical implementation stuff, be it using VHDL or something
    else.

    Now, it's still not clear if you're talking simulation or
    synthesizable code. If all you want is a clock for simulation, just
    set your simulator to picosecond resolution and use

    clk0 <= not clk0 after 54253 ns;

    which isn't exact but is close. Make sure you initialize your signal.

    But assuming you need a synthesizable solution:

    clk0 is exactly 1/12th the frequency of clk1. The canonical way of
    creating this (through logic) is with a counter (counting at clk1
    rate) that goes from 0 through 5 (hence a divide by six), toggling a
    flop every time it rolls over, giving you a 50% duty cycle square
    wave, which you can use as clk0. I *really* hope you already knew
    this.

    To generate an 18.432 MHz clock using simple sequential and
    combinatorial logic directly from 50 MHz is easy, if you can live with
    one clock cycle (20 ns) of jitter. The ratio is 1152/3125, so you
    have a 12 bit counter (holds 3125 < 4096), increment it by 1152 every
    clock, and if it exceeds 3125, you subtract off 3125. This gives you
    a modulo-3125 counter, and the MSB of this counter toggles at a 18.432
    MHz rate. There are other methods, but I suspect this is all moot, as
    I'll explain next.

    Why? You probably can't live with 20 ns of jitter. For anything
    related to audio, you usually want a "real" clock, (one which isn't
    jittered by 20ns!). This typically means you'll need to instantiate a
    PLL configuration inside the FPGA. I have no Altera experience, but I
    suspect there's some kind of GUI software wizard that will let you
    type in the two frequencies and creates a block of code that you can
    instantiate inside the FPGA.

    For Altera-speicic clock module help, you should look to Altera's
    website or an fpga newsgroup, as there's nothing VHDL specific there
    until you get the PLL code. There are many more neat ways to generate
    clocks using counters (like a power-of-two based NCO) but again, you
    have to understand what you want to build *first*, then you can ask
    how to code it in VHDL.

    Regards,

    - Kenn
     
    , Apr 17, 2008
    #6
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Skybuck Flying

    Maximum clock frequency ?

    Skybuck Flying, Aug 2, 2005, in forum: VHDL
    Replies:
    20
    Views:
    5,527
    Colonel Forbin
    Aug 10, 2005
  2. Skybuck Flying

    Re: Maximum clock frequency ?

    Skybuck Flying, Aug 2, 2005, in forum: VHDL
    Replies:
    0
    Views:
    561
    Skybuck Flying
    Aug 2, 2005
  3. x1
    Replies:
    9
    Views:
    322
    Rick DeNatale
    Oct 12, 2006
  4. PerlFAQ Server
    Replies:
    0
    Views:
    210
    PerlFAQ Server
    Feb 1, 2011
  5. PerlFAQ Server
    Replies:
    0
    Views:
    200
    PerlFAQ Server
    Mar 26, 2011
Loading...

Share This Page