# clock multiplier with factor 1.5 or 3

Discussion in 'VHDL' started by Intec, Sep 19, 2007.

1. ### Intec

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Sep 19, 2007
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Hi,

I'm using a Spartan IIe for my design.
One of the tasks is to create a high precision clock of 12.288 MHz out of 40.96MHz. As you can easily see there' a factor of 3.333 between the two frequencies.

That's the point were the problem comes in: Because of the fact that the output mustn't jitter fractional division can't be used to solve the problem.

So my idea was to use the on board DLLs of the Spartan IIe and do the following:

Divide the input frequency of 40.96MHz by 2.5 with the help of a DLL to 16.384 MHZ.
Divide this frequeny again to get 8.192MHz or 4.096 MHz.
After that use the phase shifted outputs and combine them to get an output frequency of 12.288 MHz.

So far the theory but my problem is that the on board DLLs only allow phase shifting in steps of 90° but I need 120° to solve my problem.

Is there any good idea how to solve that problem or another good approach to multiply the frequency by 1.5 or 3?

Any suggest is very welcomed !!!

Regards Christian

Intec, Sep 19, 2007

2. ### scottcarl

Joined:
May 4, 2007
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Location:
USA
Intec,
I can see your difficulty in obtaining the 12.288MHz clock frequency since the internal Xilinx DCM won't allow an output that slow (32MHz minimum, CoreGen rejects it when using a clkFX) and it also creates some jitter. Is there any way you can switch to an Altera part? They use analog PLLs (no jitter added) instead of the digital DCMs which always induce jitter. Also on the DCM creation in CoreGen there is a Phase_Shift number that allows you to roughly match the phase shift you require. So for 40.96MHz it shows a range of 0 to 73 which means you have 360/73=4.9 degrees of phase shifting precision.
Alas, I'm not sure why you have such a tight jitter requirement on a clock that is running so incredibly slow (12.288MHz). What are you actually using this for because it sounds like it's time to upgrade your technology.

Regards,
Scott

scottcarl, Sep 20, 2007

3. ### Intec

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Sep 19, 2007
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Hi Scott,

thanks for the suggest but at all there's no chance to switch to an altera part at the moment because the hardware design of the pcb is already done.

See the problem is, that the FPGA is part of a test device for telecommunication in SHDSL. For this reason we have to stick to the conventions given by the SHDSL specification which asks for a min. accuracy of 60ppm !! Otherwise will have synchronisation problems.

Maybe I have to take a closer look at the corgen and see what I can there. Up to now I tried to work with the DDS core that's also provided but without good success.

Seems as if in this case clock multiplying with the factor 3 is no trivial problem that can be solved easiliy by using the SPARTAN IIE of Xilinx.

Anywhre if there' re are any other good ideas...

Thanks

Christian

Intec, Sep 20, 2007