clock root in synthesis

[vipan]

Hi,

I have a synthesized (netlist) block called "block_A". I have put a
constraint on the port "clk_A" during the synthesis of the block_A. Now,
I want to use this synthesized block in upper level block, which doesn't
have the "clk_A" port on it, but I would like to constrain it at this level.
I used the following command in Ambit (using hierarchy):


But, it doesn't seem to work. I would appreciate if somebody helps me in
this.

Also, what is the equivalent command in SYNOPSYS.


Regards,
Vipan