clock root in synthesis

Discussion in 'VHDL' started by vipan, Sep 20, 2004.

  1. vipan

    vipan Guest

    Hi,

    I have a synthesized (netlist) block called "block_A". I have put a
    constraint on the port "clk_A" during the synthesis of the block_A. Now,
    I want to use this synthesized block in upper level block, which doesn't
    have the "clk_A" port on it, but I would like to constrain it at this level.
    I used the following command in Ambit (using hierarchy):

    >>> set_clock_root -clock clock_name -pos {block_A/clk_A}
    >>> set_clock_insertion_delay -source -pin {block_A/clk_A}



    But, it doesn't seem to work. I would appreciate if somebody helps me in
    this.

    Also, what is the equivalent command in SYNOPSYS.


    Regards,
    Vipan
    vipan, Sep 20, 2004
    #1
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