Clock task from Verilog to VHDL

Discussion in 'VHDL' started by Karper1986, May 21, 2009.

  1. Karper1986

    Karper1986

    Joined:
    May 14, 2009
    Messages:
    2
    Hello, how can I declare from verilog -->> to VHDL
    initial
    clk = 1'b0;
    always
    clk = #10 ~clk;


    And these
    `define RESET_TIME 8

    initial
    reset = 1'b1;
    task reset;
    begin
    reset <= #1 1'b1;
    tk_wait(`RESET_TIME);
    reset <= #1 1'b0;

    task tk_wait;
    input[31] count;
    integer i;
    begin
    for(i=0;i<=count;i=i+1)
    @(posedge clk);
    end
    endtask


    Anybody, please help me in solution these a little problem, cause I`m new in VHDL. THANKS
     
    Karper1986, May 21, 2009
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Valentin Tihomirov

    Are clock and divided clock synchronous?

    Valentin Tihomirov, Oct 23, 2003, in forum: VHDL
    Replies:
    11
    Views:
    3,392
    louis lin
    Oct 28, 2003
  2. Davy
    Replies:
    4
    Views:
    7,403
  3. masini
    Replies:
    0
    Views:
    1,389
    masini
    Apr 5, 2006
  4. FPGA

    Task in verilog

    FPGA, Apr 9, 2008, in forum: VHDL
    Replies:
    5
    Views:
    6,385
    Tricky
    Apr 14, 2008
  5. pierpaolo.bagnasco@gmail.com

    Generating a 78MHz clock from a 100MHz base clock (VHDL)

    pierpaolo.bagnasco@gmail.com, Nov 11, 2012, in forum: VHDL
    Replies:
    5
    Views:
    787
Loading...

Share This Page