Clocked Delay in VHDL

Discussion in 'VHDL' started by jra@febo.com, Dec 18, 2005.

  1. Guest

    Hi --

    I'm trying to create a VHDL module that acts as a clocked delay line.
    There are two inputs -- SIG and CLK -- and one output -- RESULT.

    I want all clock transitions on SIG (both positive and negative) to be
    delayed by CLK cycles and then assigned to RESULT. The delay will very
    likely be longer than the pulse width of SIG (but obviously shorter
    than the repetition rate).

    For example SIG may be a 100us long pulse repeating every second. CLK
    could be 100kHz. The requirement may be to delay SIG by 1ms. There is
    no system clock available to provide a calibrated delay; I need to use
    the CLK signal which is being derived within the CPLD (and which is not
    related to the global clock in the chip/.

    I've spent the afternoon playing with this, and can get the rising edge
    to delay the way I want it to. But when SIG falls, RESULT does not
    follow. I suspect this is because my simple process is is looping
    through its delay when SIG falls, and therefore the transition is
    missed.

    Any suggestions on how to implement this would be greatly appreciated.

    Thanks,

    John
     
    , Dec 18, 2005
    #1
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