clocked for loop with conditional if...

Discussion in 'VHDL' started by shift_1_11, Sep 10, 2009.

  1. shift_1_11

    shift_1_11

    Joined:
    Sep 10, 2009
    Messages:
    1
    I think this gets synthesized into a priority encoder, muxing the appropriate prioritised input to output (assume input is an array of some type, with the type being the same as output) and req is a an array of request signals. req(0) has the highest priority and req(2) the lowest. I think this saves a rather large amount of if..elsif's as an alternative to encode priority? >> Anyone else agree?...Im just puzzling it to myself.

    ......
    elsif (clk'event and (clk = '1')) then

    for priority in 0 to 2 loop

    if (req(priority) ='1') then
    output <= input(priority);
    end if;

    end loop;
     
    shift_1_11, Sep 10, 2009
    #1
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