clocking muxing, plz throw some light

[sudeepts]

Hello , can any one plz advise me on the correct method of handling
multiple clocks in a design, i have read many documents on clock
synchronization from Clifford E. Cummings and some SNUG papers, they
are stressing on using synchronisers for avoiding metastability, but
what i want to know is if i want to select diffirent clock rates
depneding upon some condition how do i do that using muxes which might
in turn add clock skew and glitches b/w when changing different rates.
ex coding...sytle

clk1 <= clk_1 when rate_in = "0001" else
clk_2 when rate_in = "0010" else
clk_3 when rate_in = "0011" else
clk_4 when rate_in = "0100" else
clk_5 when rate_in = "0101" else
clk_6 when rate_in = "0110" else
clk_7 when rate_in = "0111" else
clk_8 when rate_in = "1000" else
clk_9;

is this the correct way or what is the correct way to do this kind of
clock selection depending upon some condition in the design.

 

[wim.aerts01]

Hi,

If you are using FPGA's, I would not advice you to change the clock for
a particular piece of hardware. This will indeed introduce clock skew,
but more importantly you will give yourself a very hard job during
place and route (because you have to add a lot of constraints and if
not done correctly you will have image dependent results).

The easiest solution:
If you have 9 clocks, generate the hardware 9 times (each one with a
different clock). So for every condition you will have 9 results and it
is up to you to select the correct one (of course with correct
synchronisation).

good luck