clocking on a variable

Discussion in 'VHDL' started by Ralf Hildebrandt, Jun 19, 2004.

  1. Hi all!

    I just want to hear some opinions about the following (illegal) construct:


    process(sig_A,sig_B)
    variable clock : std_ulogic;
    begin
    clock:=sig_A XOR sig_B;
    if rising_edge(clock) then
    -- do something
    end if;
    end process;


    As I said this is forbidden, because only clocking on a signal is
    allowed. My question is: Why? Is it "weak point" in VHDL? Could this be
    allowed in the next VHDL standard?


    The reason for this construct is just better readable code. Within an
    architecture of 1000+ lines of code, dozens of signal are used.
    Sometimes similar signals are needed for several registers. Therefore
    signal names grow bigger (to make the code readable) and the number of
    signals grows. Especially for register-individual clock-gating (to save
    power) it would be useful to eliminate all these signals and convert
    them to variables.


    Ralf
    Ralf Hildebrandt, Jun 19, 2004
    #1
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