"Clockless" computing

[Harold Aptroot]

This isn't really a VHDL question, but I'm not sure where else to ask it.

I'm considering designing a system using only the following building blocks
(and wires and memory cells):

1:
in || out
c | v || x | y
0 | 0 || 0 | 0
0 | 1 || 0 | 0
1 | 0 || 0 | 1
1 | 1 || 1 | 0

2:
in || out
x | y || c | v
0 | 0 || 0 | ?
0 | 1 || 1 | 1
1 | 0 || 1 | 0
1 | 1 || 0 | ?

(? represents "don't care")

The C is supposed to be connected to an X or Y or C, V is should be
connected to V.
C represents the "clock" that is explicitly passed around. X and Y encode 0
and 1 respectively.
The purpose of block type 1 is doing the main calculations, block 2 takes a
result and turns it into a pair of (clock, value).
One motivation for this system is that the block type 1 directly encodes a
node from a (reduced) binary decision diagram, which are easy to manipulate.

I know it's "logically complete" in the sense that I could compute anything
with those blocks, but is it also a good way? Are there better ways?

 

[backhus]

This isn't really a VHDL question, but I'm not sure where else to ask it.

I'm considering designing a system using only the following building blocks
(and wires and memory cells):

1:
in || out
c | v || x | y
0 | 0 || 0 | 0
0 | 1 || 0 | 0
1 | 0 || 0 | 1
1 | 1 || 1 | 0

2:
in || out
x | y || c | v
0 | 0 || 0 | ?
0 | 1 || 1 | 1
1 | 0 || 1 | 0
1 | 1 || 0 | ?

(? represents "don't care")

The C is supposed to be connected to an X or Y or C, V is should be
connected to V.
C represents the "clock" that is explicitly passed around. X and Y encode 0
and 1 respectively.
The purpose of block type 1 is doing the main calculations, block 2 takes a
result and turns it into a pair of (clock, value).
One motivation for this system is that the block type 1 directly encodes a
node from a (reduced) binary decision diagram, which are easy to manipulate.

I know it's "logically complete" in the sense that I could compute anything
with those blocks, but is it also a good way? Are there better ways?

Hi Harold,
in this group and also in the rest of the net you find various
informations when you look for "asynchronous logic" design.
There are many projects and papers covering this topic.

A starting point for your investigations may be this one, if you don't
know it already:
http://en.wikipedia.org/wiki/C-element

Have a nice synthesis
Eilert