Coding error

Discussion in 'VHDL' started by Vasudevan Subramaniam, Dec 9, 2003.

  1. hi,

    here is a structural code for JKflipflop. when I simulate this it is
    not running after 20 ns. and in command window I received a message
    like this:

    # Iteration limit reached. Possible zero delay oscillation. See the
    manual.

    can anyone explain me what went wrong with this?


    --***************Norgate*******************

    library ieee;
    use ieee.std_logic_1164.all;

    entity nor1 is
    port(a,b:in std_logic;
    c:eek:ut std_logic);
    end nor1;

    architecture ar_nor1 of nor1 is
    begin
    process(a,b)
    begin
    c<=not(a AND b);
    end process;
    end;


    --**************And Gate***************

    library ieee;
    use ieee.std_logic_1164.all;

    entity and1 is
    port(a,b,clk:in std_logic;
    c:eek:ut std_logic);
    end and1;

    architecture ar_and1 of and1 is
    begin
    process(a,b,clk)
    begin
    c<=a and b and clk;
    end process;
    end;


    --***************JK FF GATE LEVEL MODEL*******************
    --2 input nor & 3 input and is copied as component

    library ieee;
    use ieee.std_logic_1164.all;

    entity jkff is
    port(j,k,clk:in std_logic;
    q,qa:eek:ut std_logic);
    end jkff;

    architecture ar_jkff of jkff is
    component nor1
    port(a,b:in std_logic;
    c:eek:ut std_logic);
    end component;
    component and1
    port(a,b,clk:in std_logic;
    c:eek:ut std_logic);
    end component;
    signal q1,qa1:std_logic;
    signal t11,t12:std_logic;
    begin
    and11:and1 port map(K,q1,clk,t11);
    and12:and1 port map(J,qa1,clk,t12);
    nor11:nor1 port map(t11,qa1,q1);
    nor12:nor1 port map(t12,q1,qa1);
    q<=q1;
    qa<=qa1;
    end;

    -------test bench
    library ieee;
    use ieee.std_logic_1164.all;
    entity tb_jkff is
    end tb_jkff;
    architecture ar_jkff of tb_jkff is
    component jkff
    port(j,k,clk:in std_logic;
    q,qa:eek:ut std_logic);
    end component;
    signal j1,k1,clk1,q1,qa1:std_logic;
    begin
    u1:jkff port map(j1,k1,clk1,q1,qa1);
    process
    begin
    j1<='0';wait for 50 ns;
    j1<='1';wait for 60 ns;
    end process;
    process
    begin
    k1<='1';wait for 40 ns;
    k1<='0';wait for 50 ns;
    end process;

    process
    begin
    clk1<='1';wait for 10 ns;
    clk1<='0';wait for 10 ns;
    end process;
    end;
     
    Vasudevan Subramaniam, Dec 9, 2003
    #1
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  2. From the error message I think you have a not a synchronous design.
    A part in your description is :

    architecture ar_and1 of and1 is
    begin
    process(a,b,clk)
    begin
    c<=a and b and clk;
    end process;
    end;

    Notice that this is not an edge triggered element as should be for a
    JK-flipflop.
    In this process if clk is '1' changes of a and/or b influence the output c
    directly
    (no rising/falling edge of clk is required).

    You could try to write the JK-flipflop in a more behavioural way, like:
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    ENTITY jkff IS
    PORT (j,k,clk : IN std_logic;
    q,qn : OUT std_logic);
    END jkff;

    ARCHITECTURE behaviour OF jkff IS
    SIGNAL qi : std_logic;
    BEGIN
    PROCESS(clk)
    VARIABLE jk : std_logic_vector(1 DOWNTO 0);
    BEGIN
    IF rising_edge(clk) THEN
    jk := j&k;
    CASE jk IS
    WHEN "00" => qi <= qi;
    WHEN "01" => qi <= '0';
    WHEN "10" => qi <= '1';
    WHEN OTHERS => qi <= NOT qi;
    END CASE;
    END IF;
    END PROCESS;
    q <= qi;
    qn <= not qi;
    END behaviour;

    Egbert Molenkamp

    "Vasudevan Subramaniam" <> wrote in message
    news:...
    > hi,
    >
    > here is a structural code for JKflipflop. when I simulate this it is
    > not running after 20 ns. and in command window I received a message
    > like this:
    >
    > # Iteration limit reached. Possible zero delay oscillation. See the
    > manual.
    >
    > can anyone explain me what went wrong with this?
    >
    >
    > --***************Norgate*******************
    >
    > library ieee;
    > use ieee.std_logic_1164.all;
    >
    > entity nor1 is
    > port(a,b:in std_logic;
    > c:eek:ut std_logic);
    > end nor1;
    >
    > architecture ar_nor1 of nor1 is
    > begin
    > process(a,b)
    > begin
    > c<=not(a AND b);
    > end process;
    > end;
    >
    >
    > --**************And Gate***************
    >
    > library ieee;
    > use ieee.std_logic_1164.all;
    >
    > entity and1 is
    > port(a,b,clk:in std_logic;
    > c:eek:ut std_logic);
    > end and1;
    >
    > architecture ar_and1 of and1 is
    > begin
    > process(a,b,clk)
    > begin
    > c<=a and b and clk;
    > end process;
    > end;
    >
    >
    > --***************JK FF GATE LEVEL MODEL*******************
    > --2 input nor & 3 input and is copied as component
    >
    > library ieee;
    > use ieee.std_logic_1164.all;
    >
    > entity jkff is
    > port(j,k,clk:in std_logic;
    > q,qa:eek:ut std_logic);
    > end jkff;
    >
    > architecture ar_jkff of jkff is
    > component nor1
    > port(a,b:in std_logic;
    > c:eek:ut std_logic);
    > end component;
    > component and1
    > port(a,b,clk:in std_logic;
    > c:eek:ut std_logic);
    > end component;
    > signal q1,qa1:std_logic;
    > signal t11,t12:std_logic;
    > begin
    > and11:and1 port map(K,q1,clk,t11);
    > and12:and1 port map(J,qa1,clk,t12);
    > nor11:nor1 port map(t11,qa1,q1);
    > nor12:nor1 port map(t12,q1,qa1);
    > q<=q1;
    > qa<=qa1;
    > end;
    >
    > -------test bench
    > library ieee;
    > use ieee.std_logic_1164.all;
    > entity tb_jkff is
    > end tb_jkff;
    > architecture ar_jkff of tb_jkff is
    > component jkff
    > port(j,k,clk:in std_logic;
    > q,qa:eek:ut std_logic);
    > end component;
    > signal j1,k1,clk1,q1,qa1:std_logic;
    > begin
    > u1:jkff port map(j1,k1,clk1,q1,qa1);
    > process
    > begin
    > j1<='0';wait for 50 ns;
    > j1<='1';wait for 60 ns;
    > end process;
    > process
    > begin
    > k1<='1';wait for 40 ns;
    > k1<='0';wait for 50 ns;
    > end process;
    >
    > process
    > begin
    > clk1<='1';wait for 10 ns;
    > clk1<='0';wait for 10 ns;
    > end process;
    > end;
     
    Egbert Molenkamp, Dec 9, 2003
    #2
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  3. Vasudevan Subramaniam

    Jim Lewis Guest

    Vasudevan,
    Two things:
    1) You have written a model without
    propagation delay. None of the real world
    devices work without propagation delay.

    2) I suspect you also have a logic bug as
    the simuloator is telling you that your circuit
    never stabilizes. I see at least one in your
    comments, the entity you call nor is really
    a nand.

    The simulator has a special trap for when a
    simulation has no delay and does not stabilize
    within a reasonable amount of time. The reasonable
    amount of time they pick is called the interation
    limit and I believe you can change it in the simulation
    options window, but I don't think this will help.

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~




    Vasudevan Subramaniam wrote:
    > hi,
    >
    > here is a structural code for JKflipflop. when I simulate this it is
    > not running after 20 ns. and in command window I received a message
    > like this:
    >
    > # Iteration limit reached. Possible zero delay oscillation. See the
    > manual.
    >
    > can anyone explain me what went wrong with this?
    >
    >
    > --***************Norgate*******************
    >
    > library ieee;
    > use ieee.std_logic_1164.all;
    >
    > entity nor1 is
    > port(a,b:in std_logic;
    > c:eek:ut std_logic);
    > end nor1;
    >
    > architecture ar_nor1 of nor1 is
    > begin
    > process(a,b)
    > begin
    > c<=not(a AND b);
    > end process;
    > end;
    >
    >
    > --**************And Gate***************
    >
    > library ieee;
    > use ieee.std_logic_1164.all;
    >
    > entity and1 is
    > port(a,b,clk:in std_logic;
    > c:eek:ut std_logic);
    > end and1;
    >
    > architecture ar_and1 of and1 is
    > begin
    > process(a,b,clk)
    > begin
    > c<=a and b and clk;
    > end process;
    > end;
    >
    >
    > --***************JK FF GATE LEVEL MODEL*******************
    > --2 input nor & 3 input and is copied as component
    >
    > library ieee;
    > use ieee.std_logic_1164.all;
    >
    > entity jkff is
    > port(j,k,clk:in std_logic;
    > q,qa:eek:ut std_logic);
    > end jkff;
    >
    > architecture ar_jkff of jkff is
    > component nor1
    > port(a,b:in std_logic;
    > c:eek:ut std_logic);
    > end component;
    > component and1
    > port(a,b,clk:in std_logic;
    > c:eek:ut std_logic);
    > end component;
    > signal q1,qa1:std_logic;
    > signal t11,t12:std_logic;
    > begin
    > and11:and1 port map(K,q1,clk,t11);
    > and12:and1 port map(J,qa1,clk,t12);
    > nor11:nor1 port map(t11,qa1,q1);
    > nor12:nor1 port map(t12,q1,qa1);
    > q<=q1;
    > qa<=qa1;
    > end;
    >
    > -------test bench
    > library ieee;
    > use ieee.std_logic_1164.all;
    > entity tb_jkff is
    > end tb_jkff;
    > architecture ar_jkff of tb_jkff is
    > component jkff
    > port(j,k,clk:in std_logic;
    > q,qa:eek:ut std_logic);
    > end component;
    > signal j1,k1,clk1,q1,qa1:std_logic;
    > begin
    > u1:jkff port map(j1,k1,clk1,q1,qa1);
    > process
    > begin
    > j1<='0';wait for 50 ns;
    > j1<='1';wait for 60 ns;
    > end process;
    > process
    > begin
    > k1<='1';wait for 40 ns;
    > k1<='0';wait for 50 ns;
    > end process;
    >
    > process
    > begin
    > clk1<='1';wait for 10 ns;
    > clk1<='0';wait for 10 ns;
    > end process;
    > end;
     
    Jim Lewis, Dec 9, 2003
    #3
  4. (Vasudevan Subramaniam) wrote:
    > here is a structural code for JKflipflop. when I simulate this it is
    > not running after 20 ns. and in command window I received a message
    > like this:
    >
    > # Iteration limit reached. Possible zero delay oscillation. See the
    > manual.
    >
    > can anyone explain me what went wrong with this?


    Yes, if you would write the code in one architecture you would clearly
    see, that you wrote something like:

    y<=a xor b;
    b<=a xor y;

    This is called combinational feedback loop.
    These signals will update every delta without 1 fs passing by. Your
    simulator will stop after a given number of deltas because per
    definition you could have unlimited delta within 1 fs.
    You have two possibilities:
    1. avoid feedback loops (sometimes very silly because your design may
    need feedback loops)
    2. use transport delay for combinational signals modeling a gate
    y<=a xor b after 2 ns;

    bye Thomas
     
    Thomas Stanka, Dec 10, 2003
    #4
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