Coding for CPLD vs FPGA

Discussion in 'VHDL' started by axr0284, Feb 5, 2008.

  1. axr0284

    axr0284 Guest

    Hi,
    I was wondering if there are any general rules when coding for a CPLD
    versus an FPGA. Thanks,
    Amish
    axr0284, Feb 5, 2008
    #1
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  2. axr0284 wrote:
    > Hi,
    > I was wondering if there are any general rules when coding for a CPLD
    > versus an FPGA. Thanks,


    CPLDs are sometimes faster for simple blocks.
    They often have fewer flops and no block ram.
    But it's just another target device for synthesis.
    It either fits and makes Fmax, or it doesn't.
    I don't change coding style.

    -- Mike Treseler
    Mike Treseler, Feb 5, 2008
    #2
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  3. axr0284

    axr0284 Guest

    On Feb 5, 1:25 pm, Mike Treseler <> wrote:
    > axr0284 wrote:
    > > Hi,
    > >  I was wondering if there are any general rules when coding for a CPLD
    > > versus an FPGA. Thanks,

    >
    > CPLDs are sometimes faster for simple blocks.
    > They often have fewer flops and no block ram.
    > But it's just another target device for synthesis.
    > It either fits and makes Fmax, or it doesn't.
    > I don't change coding style.
    >
    >        -- Mike Treseler


    Thanks for the answer.
    Amish
    axr0284, Feb 6, 2008
    #3
  4. axr0284

    Guest

    I'm not officially affiliated with Xilinx, but Xilinx Education does
    have a course for coding for CPLDs... check out Xilinx education on
    the Xilinx website if you're interested.

    On Feb 7, 12:10 am, axr0284 <> wrote:
    > On Feb 5, 1:25 pm, Mike Treseler <> wrote:
    >
    > > axr0284 wrote:
    > > > Hi,
    > > >  I was wondering if there are any general rules when coding for a CPLD
    > > > versus an FPGA. Thanks,

    >
    > > CPLDs are sometimes faster for simple blocks.
    > > They often have fewer flops and no block ram.
    > > But it's just another target device for synthesis.
    > > It either fits and makes Fmax, or it doesn't.
    > > I don't change coding style.

    >
    > >        -- Mike Treseler

    >
    > Thanks for the answer.
    > Amish
    , Feb 7, 2008
    #4
  5. axr0284

    Guest

    On Feb 5, 10:55 am, axr0284 <> wrote:
    > Hi,
    > I was wondering if there are any general rules when coding for a CPLD
    > versus an FPGA. Thanks,
    > Amish


    I have found that some vendor-bundled CPLD synthesis tools are
    sensitive to entity complexity and size. So, for the CPLD with say 4
    physical regions you might break your design apart into smaller
    chunks. I have seen cases where the same design coded 2 different
    ways is the difference between fits or doesn't fit. There are likely
    some performance implications but I didn't look into that. If you
    have good synthesis tools then this is probably less of an issue.

    -Bryce Bolton
    , Feb 20, 2008
    #5
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