Combinational feedback loops

Discussion in 'VHDL' started by john, Apr 28, 2006.

  1. john

    john Guest

    Hello, I am getting 47 cominational feedback loops for the section of
    my code that I am attaching with this message. I am using QuartusII.
    Would anyone advice me that how to get rid of these combinational feed
    back loops. I have Else for every IF/Else construct. Please advice!

    Thanks
    John

    Process (DPR_CLK, sel_14bit_mux )
    Begin

    If (DPR_CLK 'event And DPR_CLK='1') Then

    If (sel_14bit_mux = "11") Then
    -- Frame Counter --
    Address_bus( 5 ) <= Frame_cntr(0);
    Address_bus( 6 ) <= Frame_cntr(1);
    Address_bus( 7 ) <= Frame_cntr(2);
    Address_bus( 8 ) <= Frame_cntr(3);
    Address_bus( 9 ) <= Frame_cntr(4);
    Address_bus( 10 ) <= Frame_cntr(5);
    Address_bus( 11 ) <= Frame_cntr(6);
    Address_bus( 12 ) <= Frame_cntr(7);
    Address_bus( 13 ) <= Frame_cntr(8);
    Address_bus( 14 ) <= Frame_cntr(9); Address_bus( 15
    ) <= Frame_cntr(10);
    Address_bus( 16 ) <= Frame_cntr(11);
    Address_bus( 17 ) <= Frame_cntr(12);
    Address_bus( 18 ) <= Frame_cntr(13);

    -- Channel Counter --
    Address_bus( 4 downto 0 ) <= countb_mux_datain;

    Else If ( sel_14bit_mux="00")Then
    Address_bus( 18 downto 5 ) <= TEMP;

    -- Sample Counter --
    Address_bus( 4 downto 0 ) <= countc_mux_datain;

    Else If ( sel_14bit_mux = "01") Then

    Address_bus( 5 ) <= '1';
    Address_bus( 6 ) <= '0';
    Address_bus( 7 ) <= '0';
    Address_bus( 8 ) <= '0';
    Address_bus( 9 ) <= '0';
    Address_bus( 10 ) <= '0';
    Address_bus( 11 ) <= '0';
    Address_bus( 12 ) <= '0';
    Address_bus( 13 ) <= '0';
    Address_bus( 14 ) <= '0';
    Address_bus( 15 ) <= '0';
    Address_bus( 16 ) <= '0';
    Address_bus( 17 ) <= '0';
    Address_bus( 18 ) <= '0';
    Address_bus( 4 downto 0 ) <= countb_mux_datain;


    End If;
    End If;
    End If;
    End If;
    If (DPR_CLK 'event And DPR_CLK='1')Then

    If( latch_enable ='1') Then

    TEMP <= Data_Bus;
    Else
    End If;
    End If;

    If (DPR_CLK 'event And DPR_CLK='1')Then

    If( latch_CPLD ='1') Then

    Final_Temp <= Data_Bus;
    Else

    End If;

    End If;

    If (DPR_CLK 'event And DPR_CLK='1')Then

    If( P2S_load ='1') Then

    Ser_buff(18) <= Final_Temp(0);
    Ser_buff(17) <= Final_Temp(1);
    Ser_buff(16) <= Final_Temp(2);
    Ser_buff(15) <= Final_Temp(3);
    Ser_buff(14) <= Final_Temp(4);
    Ser_buff(13) <= Final_Temp(5);
    Ser_buff(12) <= Final_Temp(6);
    Ser_buff(11) <= Final_Temp(7);
    Ser_buff(10) <= Final_Temp(8);
    Ser_buff(9) <= Final_Temp(9);
    Ser_buff(8) <= Final_Temp(10);
    Ser_buff(7) <= Final_Temp(11);
    Ser_buff(6) <= Final_Temp(12);
    Ser_buff(5) <= Final_Temp(13);
    Ser_buff(4) <= countb_mux_datain(0) ;
    --(LSB....MSB)
    Ser_buff(3) <= countb_mux_datain(1) ;
    Ser_buff(2) <= countb_mux_datain(2) ;
    Ser_buff(1) <= countb_mux_datain(3) ;
    Ser_buff(0) <= countb_mux_datain(4) ;
    Else
    End If;

    End If;
    -- Reading the counter number (New Addition) --

    If (DPR_CLK 'event And DPR_CLK='1') Then
    If (Addr_active='1') Then
    Address_bus <= "0000000000000000001";
    Else
    End If;
    End If;
     
    john, Apr 28, 2006
    #1
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  2. john wrote:
    > Hello, I am getting 47 cominational feedback loops for the section of
    > my code that I am attaching with this message.


    > Process (DPR_CLK, sel_14bit_mux )

    xxxxxxxxxxxxx delete this

    > If (DPR_CLK 'event And DPR_CLK='1') Then


    > If (DPR_CLK 'event And DPR_CLK='1')Then


    > If (DPR_CLK 'event And DPR_CLK='1')Then


    > If (DPR_CLK 'event And DPR_CLK='1')Then


    > If (DPR_CLK 'event And DPR_CLK='1') Then


    You only get one of these per process.

    -- Mike Treseler
     
    Mike Treseler, Apr 28, 2006
    #2
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  3. john

    Arnaud Guest

    The process you're using is a synchronous one. There should then only
    be the clk (and an asynchronous reset if it were existing) in the
    sensitivity list. Remove the signal sel_14bit_mux from the sensitivity
    list :

    Process (DPR_CLK)
    Begin
    ....
    end process;

    I also advise you to use case statement instead of the if, elsif in the
    first if. That would be easier to read :

    If (DPR_CLK 'event And DPR_CLK='1') Then

    case sel_14bit_mux is
    when "11" =>
    -- Frame Counter --
    ...
    when "00" =>
    ...
    when "01" =>
    ..
    when others =>

    end case;

    end if;

    Regards,

    Arnaud
     
    Arnaud, Apr 28, 2006
    #3
  4. john

    john Guest

    Hi ,

    I did change it that there will be one per process. and I am also
    keeping the DPR_CLK and Reset in the sensitivity list but the compiler
    is giving me the same combinational feedback warnings. If for example,
    I change

    If( latch_CPLD ='1') Then
    Final_Temp <= Data_Bus;
    Else
    Final_Temp <= others ( => '0' );
    End If;
    End If;

    Then I can get rid of 10 combinational loops out of 42. But I do not
    want the Final_Temp assign it to zero because of my design. The code I
    mentioned previously is controlled by a state machine.
    Please advice!
    John
     
    john, Apr 28, 2006
    #4
  5. john wrote:

    > I did change it that there will be one per process. and I am also
    > keeping the DPR_CLK and Reset in the sensitivity list but the compiler
    > is giving me the same combinational feedback warnings.


    If you are getting combinational feedback, some
    assignments have slipped outside of the
    "elsif rising_edge(clk)" clause.

    > Please advice!


    Please run a sim.

    -- Mike Treseler
     
    Mike Treseler, Apr 28, 2006
    #5
  6. john

    john Guest

    The other thing is that my vhdl program is not exactly doing what I
    want it to do. For example its not working at 20MHz but working ok for
    frequencies less than 15 MHZ. I was wondering that can combinational
    loops and ripple clock can effect the functionality of the VHDL code.
    Thanks
    john
     
    john, Apr 28, 2006
    #6
  7. john

    john Guest

    The other thing is that my vhdl program is not exactly doing what I
    want it to do. For example its not working at 20MHz but working ok for
    frequencies less than 15 MHZ. I was wondering that can combinational
    loops and ripple clock can effect the functionality of the VHDL code.
    Thanks
    john
     
    john, Apr 28, 2006
    #7
  8. john

    john Guest

    The other thing is that my vhdl program is not exactly doing what I
    want it to do. For example its not working at 20MHz but working ok for
    frequencies less than 15 MHZ. I was wondering that can combinational
    loops and ripple clock can effect the functionality of the VHDL code.
    Thanks
    john
     
    john, Apr 28, 2006
    #8
  9. john

    john Guest

    Hello,

    I am running sim but i need the solution. what should I do to remove
    the problem. can combinational feedback loops introduced the problem
    like forexample my VHDL code works for clock frequencies less than
    15Mhz but does not work for frequencies greater that 15MHz,. Please
    advice!

    John
     
    john, Apr 28, 2006
    #9
  10. john

    Dave Pollum Guest

    john wrote:
    > Hello,
    >
    > I am running sim but i need the solution. what should I do to remove
    > the problem. can combinational feedback loops introduced the problem
    > like forexample my VHDL code works for clock frequencies less than
    > 15Mhz but does not work for frequencies greater that 15MHz,. Please
    > advice!
    >
    > John


    I don't know what the "solution" is. You may want to simplify the code
    as much as possible, to try to find your "loops". I've also noticed
    that you have more "end if" statements that "if" statements. I don't
    know if that has anything to do with your problem or not. I find that
    good formatting of the source code helps me avoid mistakes like that.
    I also like schematics. Sometimes I'll do something really dumb, and a
    look at the RTL schematic will quickly show me what I've done wrong,
    especially if running a simulation leaves me confused.
    HTH
    -Dave Pollum
     
    Dave Pollum, May 1, 2006
    #10
  11. john

    john Guest

    Hi Mike,

    I did not understand completely. Did you mean that there will be only
    one

    "If (DPR_CLK 'event And DPR_CLK='1') Then" for the whole process?

    Thanks
    Regards
    John
     
    john, May 3, 2006
    #11
  12. john wrote:

    > I did not understand completely. Did you mean that there will be only
    > one
    >
    > "If (DPR_CLK 'event And DPR_CLK='1') Then" for the whole process?



    For synthesis, yes.

    -- Mike Treseler
     
    Mike Treseler, May 3, 2006
    #12
  13. john

    john Guest

    Hi,

    What about the final code for the CPLD?

    John
     
    john, May 3, 2006
    #13
  14. john wrote:

    > What about the final code for the CPLD?


    That sounds like synthesis to me.

    You can use as many processes as you like,
    but each should look something like this:
    --
    begin
    if reset = '1' then
    init_regs;
    elsif rising_edge(clock) then
    update_regs;
    end if;
    update_ports;
    end process sync_template;

    -- Mike Treseler
     
    Mike Treseler, May 3, 2006
    #14
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