combining 2 buses

Discussion in 'VHDL' started by woko, Sep 1, 2004.

  1. woko

    woko Guest

    Hi there!

    I want to combine to buses: can_ad and can_ad_ts for simulation.

    type CAN_LBUS_8BIT is array (cCAN_LBUS downto 0) of std_logic_vector
    (7 downto 0);

    can_ad : inout CAN_LBUS_8BIT
    can_ad_ts : inout STD_LOGIC_VECTOR2 ( 1 downto 0 , 7 downto 0 ))

    1. I could not find any solution to connect the to buses direkt in the
    port map of the dedicated component. -> Simulation Error

    2. I tried to write something like a function to resolve the two
    buses, but it did not work out correctly. -> Bus stucks somewhere

    Does anyone knows a solution?

    Regards,

    Wolfgang Kopp
    woko, Sep 1, 2004
    #1
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  2. woko

    ALuPin Guest

    (woko) wrote in message news:<>...
    > Hi there!
    >
    > I want to combine to buses: can_ad and can_ad_ts for simulation.
    >
    > type CAN_LBUS_8BIT is array (cCAN_LBUS downto 0) of std_logic_vector
    > (7 downto 0);
    >
    > can_ad : inout CAN_LBUS_8BIT
    > can_ad_ts : inout STD_LOGIC_VECTOR2 ( 1 downto 0 , 7 downto 0 ))
    >
    > 1. I could not find any solution to connect the to buses direkt in the
    > port map of the dedicated component. -> Simulation Error
    >
    > 2. I tried to write something like a function to resolve the two
    > buses, but it did not work out correctly. -> Bus stucks somewhere
    >
    > Does anyone knows a solution?
    >
    > Regards,
    >
    > Wolfgang Kopp



    Could you show more of your code ? Best would be the complete ...
    ALuPin, Sep 1, 2004
    #2
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