Comparing compilers

Discussion in 'VHDL' started by erik.dellamonica@gmail.com, Dec 5, 2005.

  1. Guest

    Hi group!!

    I had to compare different programming styles (behavioral, structural,
    ....) and tools and, do to this, I had to compare the output of
    different compilers (ISE and Leonardo). I've seen that all the output
    files are binary or incompatible... There is any way to view, for
    example, the RTL level produced with an indipendent viewer? Or to
    compare the binary file (*.bit) produced by ISE and Leonardo or
    others??

    Thank you!!
    ERIK
     
    , Dec 5, 2005
    #1
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  2. jtw Guest

    It looks like you are comparing apples and and raisins.

    The bit file is used to load the FPGA; it is the result of a tool following
    place and route.

    All of the standard compilers should produce a common format: edif. The
    suffix may vary (edn, edf, ...), but they are ascii, [painfully]
    human-readable files.

    The back-end tools then import these (along with optimized library elements,
    which will be in binary) and generate the appropriate output file to load
    into the FPGA. For Xilinx RAM-based parts, this is [usually] a bit. For
    other manufacturers, there will be a similar programming file. And yes,
    none of those will be compatible with each other. But it has nothing to do
    with Leonard/Precision/Synplicity/ISE.

    Now, if you want to compare the edif outputs, have fun; each tool has its
    own algorithm for naming signals. Doing a global diff is usually
    pointless.

    Now what do you really want to compare? Typically, device utilization is a
    useful parameter; another, speed. The different front-end tools
    (compilers/synthesizers) will produce varying quality of results, depending
    on the tool capabilities and how they are directed.

    JTW

    <> wrote in message
    news:...
    > Hi group!!
    >
    > I had to compare different programming styles (behavioral, structural,
    > ...) and tools and, do to this, I had to compare the output of
    > different compilers (ISE and Leonardo). I've seen that all the output
    > files are binary or incompatible... There is any way to view, for
    > example, the RTL level produced with an indipendent viewer? Or to
    > compare the binary file (*.bit) produced by ISE and Leonardo or
    > others??
    >
    > Thank you!!
    > ERIK
    >
     
    jtw, Dec 5, 2005
    #2
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  3. wrote:

    > I had to compare different programming styles (behavioral, structural,
    > ...) and tools and, do to this,


    Those coding styles work with any synthesis tool.

    > I had to compare the output of
    > different compilers (ISE and Leonardo). I've seen that all the output
    > files are binary or incompatible... There is any way to view, for
    > example, the RTL level produced with an indipendent viewer?


    Use the RTL viewer that comes with the synthesis tool.
    Here's some examples: http://home.comcast.net/~mike_treseler/

    Consider evaluating hdl simulators also.
    This is the only practical way to know that
    your code will actually do what you expect
    in synthesis.

    -- Mike Treseler
     
    Mike Treseler, Dec 5, 2005
    #3
  4. Guest

    I had to compare such compiler and tools for a simple reason. We use
    FPGA only from some month, before we have used DSP. We have write
    control and estimation algorithm at high level but sometimes we had had
    some problem.... it doesn't work! :-( Some other work group, which we
    collaborate with, had tell us that they use Leonardo without any
    problem. Therefore I'm trying to understand if the problem is because
    we are writing at too higher level or the problem is the compiler. I
    suppose that the problem is the code but I had to deepen every possible
    cause fo failure.

    Thank you!

    -- Erik Della Monica
     
    , Dec 6, 2005
    #4
  5. wrote:
    > I had to compare such compiler and tools for a simple reason. We use
    > FPGA only from some month, before we have used DSP. We have write
    > control and estimation algorithm at high level but sometimes we had had
    > some problem.... it doesn't work!


    I expect that you used a development shell or debugger
    to test your DSP code before building a release.
    The equivalent tool for HDL code is a simulator.

    :-( Some other work group, which we
    > collaborate with, had tell us that they use Leonardo without any
    > problem. Therefore I'm trying to understand if the problem is because
    > we are writing at too higher level or the problem is the compiler. I
    > suppose that the problem is the code but I had to deepen every possible
    > cause fo failure.


    A logical error in the HDL code is the best bet.
    The odds that I could write a complex hdl module flawlessly
    without simulation are very small. The odds that a synthesis
    program like Leo would make a bad netlist from good code
    are even smaller.

    -- Mike Treseler
     
    Mike Treseler, Dec 6, 2005
    #5
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