comparing frequency of two clocks

Discussion in 'VHDL' started by arant, Aug 14, 2006.

  1. arant

    arant Guest

    Hi Everyone,

    Does anyone have any idea of how to compare two reference clocks using
    completely digital logic .The problem is something like this

    There are two slow ref clocks (Khz) CLKA (rc clock) CLKB (crystal
    clock) and a fast sys_clk (pll clock) Mhz range

    If freq CLKA > freq CLKB then
    op1 = 1;
    elsif freq CLKA < freq CLKB op2 = 1
    else
    op3 = 1;
    end if;

    Eagerly awaiting some solutions
     
    arant, Aug 14, 2006
    #1
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  2. arant wrote:


    > Does anyone have any idea of how to compare two reference clocks using
    > completely digital logic .The problem is something like this
    >
    > There are two slow ref clocks (Khz) CLKA (rc clock) CLKB (crystal
    > clock) and a fast sys_clk (pll clock) Mhz range
    >
    > If freq CLKA > freq CLKB then
    > op1 = 1;
    > elsif freq CLKA < freq CLKB op2 = 1
    > else
    > op3 = 1;
    > end if;


    Just an idea - you should think about it, before you use it:

    Make two counters, one counting with CLKA and one with CLKB. Let them
    count for a while (maybe until counter A has reached hundred or
    whatever). Then check the counter values. If the values of the two
    counters are equal, the clocks have almost the same frequency. If the
    difference is one this may be because of jitter and you should assume,
    that the frequencies are even then very similar. If the difference is 2
    or greater the frequencies are different enough to decide which clock is
    faster. As you count longer the answer becomes more reliable and the
    difference of one is more likely because of jitter.


    Ralf
     
    Ralf Hildebrandt, Aug 14, 2006
    #2
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  3. arant

    jacko Guest

    arant wrote:

    > Hi Everyone,
    >
    > Does anyone have any idea of how to compare two reference clocks using
    > completely digital logic .The problem is something like this
    >
    > There are two slow ref clocks (Khz) CLKA (rc clock) CLKB (crystal
    > clock) and a fast sys_clk (pll clock) Mhz range
    >
    > If freq CLKA > freq CLKB then
    > op1 = 1;
    > elsif freq CLKA < freq CLKB op2 = 1
    > else
    > op3 = 1;
    > end if;


    frequency is 1/time, so some time has to pass to measure frequency.

    if two counters are clocked by clk a and clk b then the difference sign
    says which is faster,

    to stop over or underflow, the sys clk can be xor gated with respective
    clock to either clock both up, or both down depending on the sum being
    above or below the centre.

    the dynamic difference between the clocks could lead to the need for
    infinite precision counters :)

    cheers


    > Eagerly awaiting some solutions
     
    jacko, Aug 15, 2006
    #3
  4. arant a écrit :
    > Hi Everyone,
    >
    > Does anyone have any idea of how to compare two reference clocks using
    > completely digital logic .The problem is something like this
    >
    > There are two slow ref clocks (Khz) CLKA (rc clock) CLKB (crystal
    > clock) and a fast sys_clk (pll clock) Mhz range
    >
    > If freq CLKA > freq CLKB then
    > op1 = 1;
    > elsif freq CLKA < freq CLKB op2 = 1
    > else
    > op3 = 1;
    > end if;
    >
    > Eagerly awaiting some solutions


    For the two slow clock do :
    - start fast counter on positive edge,
    - store the counter then clear it on next negative edge of the clock.
    Set a flag signifying capture is done.

    When both flag are set, reset them and compare the two captured values.

    Pascal
     
    Pascal Peyremorte, Aug 15, 2006
    #4
  5. arant

    arant Guest

    Hi Pascal ,

    I think you are suggesting the use of a capcom unit .

    One solution that I can think of is running two parallel counters on
    the sys_clk for one period of the CLKA (count a) and CLKB (ount b) and
    comparing the count values
    Two main points :
    -------------------------------
    Clock Period measurement using a one shot pulse generator
    on both the rising and falling edges of the slow clock

    Start count on the rising edge pulse and stop and store count on the
    falling edge pulse
    of the slow clock

    if count a = count b then
    op3 = 1
    elsif count a > count b then
    op2 = 1 -- freq CLKB > freq CLKA
    else -- freq CLKB < freq CLKA
    op1 = 1
    end if

    By the way the requirement is for an SoC clock managment unit that
    generates an interrupt/event to the CPU based on the clock comparison
    operation.

    Thanks

    Pascal Peyremorte wrote:
    > arant a écrit :
    > > Hi Everyone,
    > >
    > > Does anyone have any idea of how to compare two reference clocks using
    > > completely digital logic .The problem is something like this
    > >
    > > There are two slow ref clocks (Khz) CLKA (rc clock) CLKB (crystal
    > > clock) and a fast sys_clk (pll clock) Mhz range
    > >
    > > If freq CLKA > freq CLKB then
    > > op1 = 1;
    > > elsif freq CLKA < freq CLKB op2 = 1
    > > else
    > > op3 = 1;
    > > end if;
    > >
    > > Eagerly awaiting some solutions

    >
    > For the two slow clock do :
    > - start fast counter on positive edge,
    > - store the counter then clear it on next negative edge of the clock.
    > Set a flag signifying capture is done.
    >
    > When both flag are set, reset them and compare the two captured values.
    >
    > Pascal
     
    arant, Aug 15, 2006
    #5
  6. Hi,

    arant schrieb:
    > I think you are suggesting the use of a capcom unit .
    >
    > One solution that I can think of is running two parallel counters on
    > the sys_clk for one period of the CLKA (count a) and CLKB (ount b) and
    > comparing the count values
    > Two main points :
    > -------------------------------
    > Clock Period measurement using a one shot pulse generator
    > on both the rising and falling edges of the slow clock
    >
    > Start count on the rising edge pulse and stop and store count on the
    > falling edge pulse
    > of the slow clock


    You should think about your needs. Do you need a statement about the
    length of a high pulse or a statement about the clock periode? For a
    50% duty cycle there's no difference, else you might need to stop on
    the next rising edge.

    bye Thomas
     
    Thomas Stanka, Aug 16, 2006
    #6
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