comparing the array in parallel

[srinukasam]

hello
in my design i need a logic to compare the array (suppose width 16 bit and
size of 0 to 15) with a vector of 16 bit in parallel and in one clk cycle.
and need to generate address of array is matching.

thank you
bye

 

[Ralf Hildebrandt]

in my design i need a logic to compare the array (suppose width 16 bit and
size of 0 to 15) with a vector of 16 bit in parallel and in one clk cycle.

Just model 16 comparators - each for one array row.

match_0 <= '1' when (my_array(0) = my_vector) else '0';
....

and need to generate address of array is matching.

Does the vector match only one array element or may there be more?

process(match_0, macht_1 ....)
begin
if (match_0 = '1') then
address<="0000"
elsif (match_1 = '1') then
address<="0001"
elsif ...
end if;
end process;


Note: You may eliminate the intermediate match_X signals if you combine
all statements, but this does not lead to a smaller hardware.

Ralf

 

[Me]

Homework buster.
Give directions not solutions.

A.

 

[viku]

try this but in one clock cycle u r able to compare only one address of
array with the vector;
try this codee
if rst='1'then
addr<=(others=> '0');
elsif rising_edge(clk)then
array(addr)<= vector
addr<= addr+1;
if array(addr)= vector then
found <='1';
foundaddr<=addr
else
found <='0';
foundaddr<="zzzz....z";
end if;