Comparison of Bit Vectors in a Conditional Signal Assignment Statement

[Anand P Paralkar]

Hi,

I am trying to compare two bit vectors formed by aggregating/concatenating
individual bits of a vector in a "Conditional Signal Assignment Statement"
as follows:

err <= '1' when ( (int_h_data(19), int_h_data(18), int_h_data(16),
int_h_data(12), int_h_data(4)) /=

(h_data(19), h_data(18), h_data(16), h_data(12),
h_data(4)) ) else

'0' when ( (int_h_data(19), int_h_data(18), int_h_data(16),
int_h_data(12), int_h_data(4)) =

(h_data(19), h_data(18), h_data(16), h_data(12),
h_data(4)) );

The err flag should be set to '1' when the two concatenations are not
equal and should be reset to '0' when the two concatenations are equal.

On compiling the code above, the compiler returns error messages:

int_h_data(12), int_h_data(4)) /=
|
expression is ambiguous

int_h_data(12), int_h_data(4)) =
|
expression is ambiguous

Could you please explain why?

Thanks,
Anand

 

[Egbert Molenkamp]

Anand,

I think you have to compare the concated vectors, so something like:
err <= '1' when ( i(19) & i(18) & i(16)) / = ( d(19) & d(18) & d(16))

HOWEVER .. I assume i(19) is a std_logic (std_ulogic) and if you are
using also numeric_std/std_logic_arith then there are multiple functions
"/="
possible (i.e. the ( i(19) & i(18) & i(16)) could be a std_logic_vector,
signed, unsigned).
Therefore qualification can be used:
err <= '1' when std_logic_vector'( i(19) & i(18) & i(16)) / = ( d(19) &
d(18) & d(16))

Or in this specifc case were i(19) and the next index i(18) is used you
could write;
err <= '1' when ( i(19 DOWNTO 18) & i(16)) / = ( d(19 DOWNTO 18) & d(16))
(in this case the type of the vector is still known)

Egbert Molenkamp

 

[Srinivasan Venkataramanan]

Hi Anand,
You will need to "qualify" the result of
aggregation/concatenation within your CSA.

err <= '1' when ( bit_vector'(int_h_data(19), int_h_data(18),
int_h_data(16),
int_h_data(12), int_h_data(4)) /=

bit_vector'(h_data(19), h_data(18), h_data(16),
h_data(12),
h_data(4)) ) else

'0' when ( bit_vector'(int_h_data(19), int_h_data(18),
int_h_data(16),
int_h_data(12), int_h_data(4)) =

bit_vector'(h_data(19), h_data(18), h_data(16),
h_data(12),
h_data(4)) );

I don't quite remember why (haven't been using VHDL for quite some
time), but it has to do with the fact that the result of
aggregation/concatenation is ambiguous, I hope some one else will
explain why.

Regards,
Srinivasan
http://www.noveldv.com