compilation error with ModelSim

[Vincent]

Hi,

I have the following error while trying to compile a program with Modelsim :
**Error: H:/ModelTech/OpenCore/RISCMCU/RISCMCU/vhdl/v_riscmcu.vhd(60):
Signal c must have only one source since it is connected to a buffer port.

c is a signal defined as the following : std_logic_vector(7 downto 0) and is
used for components instance later.

Do you have any idea to solve this ?

Vincent BRUYERE

 

[Jon]

Hi Vincent,
From the message it sounds like the signal "C" can be driven by
multiple components without seeing what the signal "C" is connected
to I can't tell. Make sure that "C" is only driven by a single source
so it can not be connected to two ports of type buffer.

Jon

 

[Vincent]

Hi Jon,

ok, thanks.
The signal c is declared as the following :
signal c: std_logic_vector(7 downto 0);

it is afterwards used in different components declaration :
c : in std_logic_vector(7 downto 0);
c : buffer std_logic_vector(7 downto 0);
c : inout std_logic_vector(7 downto 0);

i changed the 'buffer' type in 'in' type and it compiles...
what is buffer type and what equivalent type can be used instead ?

Vincent

 

[Jon]

Hi Vincent,
Buffer is a type of output that allows you to use the output
internally to the block. I usually recommend that people stay away
from the buffer type and if they need to use the output inside their
code that they create another signal for internal use and also assign
it to their output port.

Jon