compilation errors

Discussion in 'VHDL' started by Eqbal, Nov 18, 2003.

  1. Eqbal

    Eqbal Guest

    Hi,

    I am getting the following compilation error in my cfg file:

    use entity work.prefetch64(prefetch64_arc);
    ncvhdl_p: *E,BINCFL (rtl_pipe_cache/cfg_pcpu.vhd,56): no corresponding
    formal fo
    r local (RDYIN) in implicit map aspect [5.2.2].
    use entity work.prefetch64(prefetch64_arc);
    ncvhdl_p: *E,BINOAE (rtl_pipe_cache/cfg_pcpu.vhd,56): entity formal
    (IRDYIN) req
    uires association in implicit map aspect [5.2.2].

    Any idea on why this kind of error can occur. My files got compiled ok
    on vhdl simili, but they aren't compiling on cadence.
     
    Eqbal, Nov 18, 2003
    #1
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