Compiling VHDL to EXE

Discussion in 'VHDL' started by Arnaldo Oliveira, Jul 18, 2003.

  1. Hi,

    Is there any way to create an executable application from a VHDL project
    composed of several modules?
    The idea is to have a standalone application with the simulation kernel
    embedded and some input/output support to control the simulation and get
    signal values.
    Thank You.
    Arnaldo.
    --
    ___________________________________________________________
    Arnaldo Oliveira
    Dep. de Electrónica e Telecomunicações
    Universidade de Aveiro
    email:
     
    Arnaldo Oliveira, Jul 18, 2003
    #1
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  2. Arnaldo Oliveira

    Mario Trams Guest

    Arnaldo Oliveira wrote:

    > Hi,
    >
    > Is there any way to create an executable application from a VHDL project
    > composed of several modules?
    > The idea is to have a standalone application with the simulation kernel
    > embedded and some input/output support to control the simulation and get
    > signal values.
    > Thank You.


    Hello Arnaldo,

    I don't know whether there is a VHDL simulator that can do so
    (theoretically, it should be possible).

    But perhaps SystemC might be much more useful for your purpose
    as you have much more freedom there.

    Just check www.systemc.org.

    Regards,
    Mario
     
    Mario Trams, Jul 18, 2003
    #2
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  3. Hello Mario,

    Thank you for your suggestion. I have already worked with SystemC.
    However, my project (a processor IP core) is fully written in VHDL at RTL
    level, which means that it can be directly synthesized and implemented with
    the target technology implementation tools (in my case FPGA).
    My goal (wish) is to use the same model for implementation and simulation
    purposes.
    More precisely, I would like to create a simulator with a user friendly
    interface directly from the synthesizable VHDL source code.
    With SystemC I can easily create a behavioral model of the processor and a
    simulator but then I need some compilation tool to translate the behavioral
    model to RTL VHDL.
    That's my problem...
    Basically I wouldn't like to buy an expensive behavioral synthesis tool, if
    I already have the synthesizable VHDL model.
    Thanks anyway for you answer.

    Regards,
    Arnaldo.


    Arnaloif
    "Mario Trams" <-chemnitz.de> wrote in message
    news:bf8ss7$orb$-chemnitz.de...
    > Arnaldo Oliveira wrote:
    >
    > > Hi,
    > >
    > > Is there any way to create an executable application from a VHDL project
    > > composed of several modules?
    > > The idea is to have a standalone application with the simulation kernel
    > > embedded and some input/output support to control the simulation and get
    > > signal values.
    > > Thank You.

    >
    > Hello Arnaldo,
    >
    > I don't know whether there is a VHDL simulator that can do so
    > (theoretically, it should be possible).
    >
    > But perhaps SystemC might be much more useful for your purpose
    > as you have much more freedom there.
    >
    > Just check www.systemc.org.
    >
    > Regards,
    > Mario
    >
     
    Arnaldo Oliveira, Jul 18, 2003
    #3
  4. Arnaldo Oliveira wrote:

    > Is there any way to create an executable application from a VHDL project
    > composed of several modules?


    Hmmm. The executable application is the vhdl simulator.
    Your VHDL code is input data for the executable.

    > The idea is to have a standalone application with the simulation kernel
    > embedded and some input/output support to control the simulation and get
    > signal values.


    That defines a simulator. Writing one is a big project.

    See:
    http://www.staticfreesoft.com/manual/ElectricManual.pdf

    -- Mike Treseler
     
    Mike Treseler, Jul 18, 2003
    #4
  5. Arnaldo Oliveira

    Mario Trams Guest

    Hello Arnaldo,

    > Thank you for your suggestion. I have already worked with SystemC.
    > However, my project (a processor IP core) is fully written in VHDL at RTL
    > level, which means that it can be directly synthesized and implemented
    > with the target technology implementation tools (in my case FPGA).
    > My goal (wish) is to use the same model for implementation and simulation
    > purposes.
    > More precisely, I would like to create a simulator with a user friendly
    > interface directly from the synthesizable VHDL source code.
    > With SystemC I can easily create a behavioral model of the processor and a
    > simulator but then I need some compilation tool to translate the
    > behavioral model to RTL VHDL.
    > That's my problem...
    > Basically I wouldn't like to buy an expensive behavioral synthesis tool,
    > if I already have the synthesizable VHDL model.


    Ahh, ok. I see.
    I just made a quick google for "vhdl to systemc" and found that:
    http://www-ti.informatik.uni-tuebingen.de/~systemc/download_content.html

    There is a VHDL to SystemC converter for RTL designs.
    Perhaps that is working for your processor model as well.

    Regards,
    Mario


    --
    ----------------------------------------------------------------------
    Digital Force / Mario Trams -chemnitz.de

    Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr
    Dept. of Computer Science Tel.: (+49) 371 531 1660
    Chair of Computer Architecture Fax.: (+49) 371 531 1818
    ----------------------------------------------------------------------
     
    Mario Trams, Jul 18, 2003
    #5
  6. Hi!

    Thanks again for your suggestions :)
    Now I have two ways to try: GHDL and VHDL2SystemC converter.
    Regards,
    Arnaldo.

    "Mario Trams" <-chemnitz.de> wrote in message
    news:bf9n9g$9qc$-chemnitz.de...
    Hello Arnaldo,

    > Thank you for your suggestion. I have already worked with SystemC.
    > However, my project (a processor IP core) is fully written in VHDL at RTL
    > level, which means that it can be directly synthesized and implemented
    > with the target technology implementation tools (in my case FPGA).
    > My goal (wish) is to use the same model for implementation and simulation
    > purposes.
    > More precisely, I would like to create a simulator with a user friendly
    > interface directly from the synthesizable VHDL source code.
    > With SystemC I can easily create a behavioral model of the processor and a
    > simulator but then I need some compilation tool to translate the
    > behavioral model to RTL VHDL.
    > That's my problem...
    > Basically I wouldn't like to buy an expensive behavioral synthesis tool,
    > if I already have the synthesizable VHDL model.


    Ahh, ok. I see.
    I just made a quick google for "vhdl to systemc" and found that:
    http://www-ti.informatik.uni-tuebingen.de/~systemc/download_content.html

    There is a VHDL to SystemC converter for RTL designs.
    Perhaps that is working for your processor model as well.

    Regards,
    Mario


    --
    ----------------------------------------------------------------------
    Digital Force / Mario Trams -chemnitz.de

    Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr
    Dept. of Computer Science Tel.: (+49) 371 531 1660
    Chair of Computer Architecture Fax.: (+49) 371 531 1818
    ----------------------------------------------------------------------
     
    Arnaldo Oliveira, Jul 21, 2003
    #6
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