Complex Bit Index Syntax, does this exist?

Discussion in 'VHDL' started by Alex, Oct 16, 2006.

  1. Alex

    Alex Guest

    I'm trying to find if there's a syntax for this (this doesn't work):

    OUTPUT_BIT <= ((value1_4bit & value2_4bit) - value3_8bit) (7);

    In summary, .. in a single statement, combining two 4 bit values,
    subtracting an 8bit value from them, and getting the most significant
    bit of the result. Is there a way to synthesize this outside of a
    process statement?

    If it matters, i'm using Xilinx ISE 8.2.03i.

    Thanks,

    Alex McHale
     
    Alex, Oct 16, 2006
    #1
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  2. Alex

    Andy Guest

    Why do you need this in one statement?

    It will likely be more self-documenting and easier to maintain if you
    can use more than one statement, and put them in a function if
    necessary i.e. for an initial value, etc.

    Also, are these signed are unsigned quantities? If unsigned, is the
    result of the subtraction guaraneed to be non-negative, or do you care?


    Knowing that, I could probably come up with a cryptic expression
    (almost as cryptic as the one you tried) that would give it to you in
    one statement, but then you, and more importantly the next poor sap
    that has to maintain your design, would not know what was being done.

    Andy


    Alex wrote:
    > I'm trying to find if there's a syntax for this (this doesn't work):
    >
    > OUTPUT_BIT <= ((value1_4bit & value2_4bit) - value3_8bit) (7);
    >
    > In summary, .. in a single statement, combining two 4 bit values,
    > subtracting an 8bit value from them, and getting the most significant
    > bit of the result. Is there a way to synthesize this outside of a
    > process statement?
    >
    > If it matters, i'm using Xilinx ISE 8.2.03i.
    >
    > Thanks,
    >
    > Alex McHale
     
    Andy, Oct 16, 2006
    #2
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  3. On 16 Oct 2006 12:03:14 -0700, "Alex" <> wrote:

    >I'm trying to find if there's a syntax for this (this doesn't work):
    >
    > OUTPUT_BIT <= ((value1_4bit & value2_4bit) - value3_8bit) (7);
    >
    >In summary, .. in a single statement, combining two 4 bit values,
    >subtracting an 8bit value from them, and getting the most significant
    >bit of the result. Is there a way to synthesize this outside of a
    >process statement?


    You can't subscript an expression, only an object. Make an
    intermediate signal or variable to hold the result, and subscript
    that. It'll synthesise just as well, and as Andy said it will be
    easier to understand.

    Alternatively, if the vectors are all of SIGNED data type, you
    could simply test the result's sign:

    OUTPUT_BIT <= '1' when
    ((value1_4bit & value2_4bit) - value3_8bit) < 0
    else '0';

    and in some situations that might be even clearer.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Oct 19, 2006
    #3
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