component configuration, default binding, ModelSim

[chi]

Hello, could you please give some words on my component configuration
question. Thanks in advance.

I wrote a simple design to produce the problem. It compromises two
design file, each corresponding to an entity, named a_entity and
b_entity. b_entity includes a component to be linked to a_entity. The
two files below tell all details.

-------------------------------
file 1: a.vhd
-------------------------------
entity a_entity is

port (
a : in std_logic;
b : out std_logic);

end a_entity;

architecture sim of a_entity is

begin -- sim

b <= a;

end sim;
-------------------------------
file 2: b.vhd
-------------------------------
library ieee;
use ieee.std_logic_1164.all;


entity b_entity is
port (
a : in std_logic;
b : out std_logic);
end b_entity;

architecture sim of b_entity is

component a_entity
port (
a : in std_logic;
b : out std_logic);
end component;

begin -- sim

entity_a_0 : component a_entity
port map (
a => a,
b => b);

end sim;

library lib_a;
configuration cfg_b_entity of b_entity is

for sim
for entity_a_0 : a_entity
use entity lib_a.a_entity(sim);
end for;
end for;

end cfg_b_entity

-------------------------------
I used ModelSim 5.7e on Sun Soloris 8, with following script:
-------------------------------

if {[file exist work]} {rm -r work}
vlib work
vmap work ./work

if {[file exist lib_a ]} {rm -r lib_a }
vlib lib_a
vmap lib_a ./lib_a

if {[file exist lib_b]} {rm -r lib_b}
vlib lib_b
vmap lib_b ./lib_b

vcom -93 -work lib_a a.vhd

vcom -93 -work lib_b b.vhd

-------------------------------
ModelSim said:
-------------------------------

# Model Technology ModelSim SE vcom 5.7e Compiler 2003.07 Jul 8 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity a_entity
# -- Compiling architecture sim of a_entity

# Model Technology ModelSim SE vcom 5.7e Compiler 2003.07 Jul 8 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity b_entity
# -- Compiling architecture sim of b_entity
# WARNING[1]: b.vhd(24): No default binding for component: "a_entity".
(No entity named "a_entity" was found)
# -- Compiling configuration cfg_b_entity
# -- Loading entity b_entity
# -- Loading architecture sim of b_entity
# -- Loading entity a_entity

The question is about that Warning ModelSim issued. Now that a
component configuration specification is provided in file 2, why does
ModelSim check the default bindings? Thank you for help!

H. Chi

 

[Eyck Jentzsch]

If you look at the log fo Modelsim, you will see, that the message
originates of the compilation of your _architecture_ sim of b_entity.
The reason is that you specified:

begin -- sim

entity_a_0 : component a_entity

^^^^^^^^^
This is a dircet instantiation and direct instantiation serves as
component declaration and configuration specification. With this direct
instantiation you said, that anything that fits into this 'socket'
should be used and this is the behavior of default binding...
Change the line to:

entity_a_0 : a_entity

-it's also valid VHDL93- and your warning is gone
HTH

-Eyck

 

[Jim Lewis]

Chi,

# WARNING[1]: b.vhd(24): No default binding for component: "a_entity".
(No entity named "a_entity" was found)

You will note this is a warning. In your case in particular
this is not an error since you have the configuration.
As long as you simulate the configuration you are fine.

The warning happened when you compiled b.vhd.
It says that when you compiled b, the compiler could not
default bind a_entity (because lib_a was not visible).
The warning indicates that your design will need some other
means to bind a_entity or it will be unbound.
Since you have the configuration, you are ok.
If you tried to simulate b_entity without the configuration,
you would find that a_entity is unbound.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Hello, could you please give some words on my component configuration
question. Thanks in advance.

I wrote a simple design to produce the problem. It compromises two
design file, each corresponding to an entity, named a_entity and
b_entity. b_entity includes a component to be linked to a_entity. The
two files below tell all details.

-------------------------------
file 1: a.vhd
-------------------------------
entity a_entity is

port (
a : in std_logic;
b : out std_logic);

end a_entity;

architecture sim of a_entity is

begin -- sim

b <= a;

end sim;
-------------------------------
file 2: b.vhd
-------------------------------
library ieee;
use ieee.std_logic_1164.all;


entity b_entity is
port (
a : in std_logic;
b : out std_logic);
end b_entity;

architecture sim of b_entity is

component a_entity
port (
a : in std_logic;
b : out std_logic);
end component;

begin -- sim

entity_a_0 : component a_entity
port map (
a => a,
b => b);

end sim;

library lib_a;
configuration cfg_b_entity of b_entity is

for sim
for entity_a_0 : a_entity
use entity lib_a.a_entity(sim);
end for;
end for;

end cfg_b_entity

-------------------------------
I used ModelSim 5.7e on Sun Soloris 8, with following script:
-------------------------------

if {[file exist work]} {rm -r work}
vlib work
vmap work ./work

if {[file exist lib_a ]} {rm -r lib_a }
vlib lib_a
vmap lib_a ./lib_a

if {[file exist lib_b]} {rm -r lib_b}
vlib lib_b
vmap lib_b ./lib_b

vcom -93 -work lib_a a.vhd

vcom -93 -work lib_b b.vhd

-------------------------------
ModelSim said:
-------------------------------

# Model Technology ModelSim SE vcom 5.7e Compiler 2003.07 Jul 8 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity a_entity
# -- Compiling architecture sim of a_entity

# Model Technology ModelSim SE vcom 5.7e Compiler 2003.07 Jul 8 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity b_entity
# -- Compiling architecture sim of b_entity
# WARNING[1]: b.vhd(24): No default binding for component: "a_entity".
(No entity named "a_entity" was found)
# -- Compiling configuration cfg_b_entity
# -- Loading entity b_entity
# -- Loading architecture sim of b_entity
# -- Loading entity a_entity

The question is about that Warning ModelSim issued. Now that a
component configuration specification is provided in file 2, why does
ModelSim check the default bindings? Thank you for help!

H. Chi

 

[sreeram]

similar problem of component not bound in model sim

I have a VHDL program, a package and a test bench.
I have a problem in using the Xilinx ISE8.2i version similar to the one discussed here in this thread with some basic differences. Kindly suggest a solution to this problem.

Thanks in advance

Main Program:

library ieee,work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.addmain.all;

entity add is
port (reset: in std_logic;
clock: in std_logic;
a : in addvector;
b : out std_logic_vector(7 downto 0)
);
end add;

architecture add_arch of add is
begin
process (reset,clock)
begin
if (reset='1')then
b <= '00000000';
else
if (clock'event and clock='1')then
b<= '0000' & ((a.operand1) + (a.operand2));
end if; -- For 'clock'
end if; -- For 'reset'
end process;
end add_arch;

Package Program:

library ieee;
use ieee.std_logic_1164.all;

package addmain is
type addvector is record
operand1: std_logic_vector (3 downto 0);
operand2: std_logic_vector (3 downto 0);
end record;
end addmain;

Test bench Program:

library ieee,work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.addmain.all;

entity testadd is
end testadd;

architecture testadd_arch of testadd is
signal tb_reset: std_logic;
signal tb_clock: std_logic;
signal tb_a : addvector;
signal tb_b : std_logic_vector (7 downto 0);

component add
port (reset: in std_logic;
clock: in std_logic;
a : in addvector;
b : out std_logic_vector(7 downto 0)
);
end component;
begin
UUT: add port map(reset=>tb_reset,
clock=>tb_clock,
a=>tb_a,
b=>tb_b);
clkrocess
begin
tb_clock <= '0';
wait for 50 ns;
tb_clock <= '1';
wait for 50 ns;
end process clk;

process
begin
tb_reset <= '1';
wait for 200 ns;
tb_reset <= '0';
tb_a.operand1 <= '0001';
tb_a.operand2 <= '0010';
wait for 400 ns;
tb_a.operand1 <= '0101';
tb_a.operand2 <= '0010';
wait for 400 ns;
wait;
end process;
end testadd_arch;

Now all my 3 files are working fine till post translate step. But when I try to go for the Post map stage some error comes…as below:
“# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Error: test-addmain.vhd(26): No default binding for component 'add'. (Port 'a' is not on the entity.)
# ** Warning: [1] (vopt-3473) Component instance 'uut : add' is not bound.
# Optimization failed
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./testadd.mdo PAUSED at line 8”