COMPONENT fjkce and warning

Discussion in 'VHDL' started by ontos, May 8, 2007.

  1. ontos

    ontos

    Joined:
    Mar 15, 2007
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    Hallo all.
    I use this component
    component fjkce
    port(CLR,CE, J,K,C:IN BIT; Q: OUT BIT);
    end component;


    And when i compile Code (Xilinx ISE), become this warning:
    WARNING:Xst:2036 - Inserting OBUF on port <q> driven by black box <fjkce>. Possible simulation mismatch.

    For example when i use fd, and3, or3... i become this warning not. With PORT declaration is all good. I click on "View Technology Schematic" to see schematic, and there it's all right. But respecting this warning i can't normaly use Wave Form Testbench, because output ist passive....
     
    ontos, May 8, 2007
    #1
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