Component Instantiation not driving outputs

Discussion in 'VHDL' started by nfirtaps, Aug 24, 2006.

  1. nfirtaps

    nfirtaps Guest

    Hello, I am creating a FIFO IP core in ISE. Everything goes well with
    the generation however when I write a small VHDL file that port maps
    the outputs and inputs to the FIFO I can see the outputs are not being
    driven. In the simulator the outputs are 'U'. Here's a little
    background before I paste in my code. The abbreviations ef and ff
    stand for empty flag (which should be '1' after the FIFO is reset), and
    full flag (which should be '0' after the fifo is reset). Here is some
    code does this look right for the port mapping and instantiation?
    Also, do I have to make signals for the port mapping, or can I directly
    use the signals in the entity description instead of have to make
    std_logic and assign them in the behavioral?

    Thanks in advance...

    entity fpga_fifo_filler is
    Port ( clk : in STD_LOGIC; -- clk that will map to the fifo
    instance
    enable : in STD_LOGIC; --enable on the fifo
    reset : in std_LOGIC; -- reset on the fifo
    fpga_fifoef : out STD_LOGIC; --the fifo empty flag
    fpga_fifoff : out STD_LOGIC); --the fifo full flag
    end fpga_fifo_filler;

    architecture Behavioral of fpga_fifo_filler is

    signal clk_wire : std_logic; --I put these here for the port map,
    signal enable_wire : std_logic; --It will also synthesize if I just map
    the enable on the entity
    signal reset_wire : std_logic; --Is it even necessary to have these
    signals?
    signal fpga_fifoef_wire : std_logic;
    signal fpga_fifoff_wire : std_logic;

    component wrapped_async_fifo
    port (
    din: IN std_logic_VECTOR(15 downto 0);
    rd_clk: IN std_logic;
    rd_en: IN std_logic;
    rst: IN std_logic;
    wr_clk: IN std_logic;
    wr_en: IN std_logic;
    dout: OUT std_logic_VECTOR(15 downto 0);
    empty: OUT std_logic;
    full: OUT std_logic);
    end component;

    begin

    Inst_wrapped_async_fifo : wrapped_async_fifo
    port map(
    din => "0000000000000000",
    rd_clk => '0',
    rd_en => '0',
    rst => reset_wire,
    wr_clk => clk_wire, --map the clk_wire and feed the clock to the
    fifo
    wr_en => enable_wire, -- map the enable ...
    dout => open,
    empty => fpga_fifoef_wire, --these signals are not driven in
    simulation why????
    full => fpga_fifoff_wire --not driven in simulation why????
    );

    --Inputs
    clk_wire <= clk; -mapping, again do I need these?
    reset_wire <= reset;
    enable_wire <= enable;

    --Outputs
    fpga_fifoef <= fpga_fifoef_wire;
    fpga_fifoff <= fpga_fifoff_wire;

    end Behavioral;
    nfirtaps, Aug 24, 2006
    #1
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  2. nfirtaps

    Arnim Guest

    Hi,

    On which simulator? Are there warnings during analyze/elaborate about
    wrapped_async_fifo not being bound?

    > however when I write a small VHDL file that port maps the outputs and
    > inputs to the FIFO I can see the outputs are not being driven. In
    > the simulator the outputs are 'U'.


    Which signals exactly? For instance, fpga_fifo_filler.fpga_fifoef_wire
    or fpga_fifo_filler.Inst_wrapped_async_fifo.empty?
    Are all inputs to Inst_wrapped_async_fifo at expected values?

    Regarding the *_wire signals, you could connect the ports of
    Inst_wrapped_async_fifo to the corresponding entity ports of
    fpga_fifo_filler. Intermediate signals are only required if you want to
    read the outputs of Inst_wrapped_async_fifo somewhere else inside
    fpga_fifo_filler.

    In fact, assigning clk to an intermediate signal generates a delta cycle
    on your clock network which might lead to unintended simulation
    behavior. You really want to avoid this unless you know exactly what
    you're doing.


    Cheers

    Arnim
    Arnim, Aug 24, 2006
    #2
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  3. nfirtaps

    nfirtaps Guest

    Arnim, thanks for your reply.

    This is on the Fuse simulator through ISE. There is a warning that
    reads:

    Warning: No entity is bound for inst

    I guess this would be my problem, I have checked the Xilinx website on
    this matter
    http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=22548

    which tells me to make sure that the .xco file has
    Synthesis/Imp+Simulation is selected, and it is. Also it tells me to
    verify that either the .v or .vhd (depending on the "View Instantiation
    Template" language setting for the core) exists in the project
    directory. I do not see a wrapped_async_fifo.vhd file anywhere but the
    instance is under my vhdl module (fpga_fifo_filler) which is named
    Inst_wrapped_async_fifo - wrapped_async_fifo. Thanks for pointing me
    to that warning? Which I would think should be an error?

    Do you have any ideas of what I do to bound this instantiation?

    Thanks,
    Lloyd




    Arnim wrote:
    > Hi,
    >
    > On which simulator? Are there warnings during analyze/elaborate about
    > wrapped_async_fifo not being bound?
    >
    > > however when I write a small VHDL file that port maps the outputs and
    > > inputs to the FIFO I can see the outputs are not being driven. In
    > > the simulator the outputs are 'U'.

    >
    > Which signals exactly? For instance, fpga_fifo_filler.fpga_fifoef_wire
    > or fpga_fifo_filler.Inst_wrapped_async_fifo.empty?
    > Are all inputs to Inst_wrapped_async_fifo at expected values?
    >
    > Regarding the *_wire signals, you could connect the ports of
    > Inst_wrapped_async_fifo to the corresponding entity ports of
    > fpga_fifo_filler. Intermediate signals are only required if you want to
    > read the outputs of Inst_wrapped_async_fifo somewhere else inside
    > fpga_fifo_filler.
    >
    > In fact, assigning clk to an intermediate signal generates a delta cycle
    > on your clock network which might lead to unintended simulation
    > behavior. You really want to avoid this unless you know exactly what
    > you're doing.
    >
    >
    > Cheers
    >
    > Arnim
    nfirtaps, Aug 24, 2006
    #3
  4. nfirtaps

    Arnim Guest


    > This is on the Fuse simulator through ISE. There is a warning that
    > reads:
    >
    > Warning: No entity is bound for inst
    >
    > I guess this would be my problem.I do not see a
    > wrapped_async_fifo.vhd file anywhere but the instance is under my
    > vhdl module (fpga_fifo_filler) which is named Inst_wrapped_async_fifo
    > - wrapped_async_fifo. Thanks for pointing me to that warning?
    > Which I would think should be an error?


    Yes, this is a very severe warning as it implies that the instance ports
    are not properly connected to the rest of the design.

    > Do you have any ideas of what I do to bound this instantiation?


    It seems to me that the default binding does not work correctly in your
    case. That's hard to diagnose without sitting in front of your machine.
    Have a look at

    http://tams-www.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html#default_binding

    Especially the paragraph that explains the "set of default binding
    rules". Basically, you could check whether all of the follwing rules are
    fulfilled in your design:

    1. entity of wrapped_async_fifo is analyzed before architecture
    of fpga_fifo_filler is analyzed (log file of the compile?)
    2. your component declaration for wrapped_async_fifo is identical
    to the corresponding entity (except formatting)
    3. *all* the component ports are actually mapped in the port map to
    "thingies" of the same type

    Issue 3 might be violated in your design, as you have an "open" mapped
    to dout and these "00.."/'0' literals mapped to other ports. I'm not
    100% sure about this, but you could try to define signals of exactly the
    same type as the component ports. Like

    signal din_wire : std_logic_VECTOR(15 downto 0);
    [...]
    din_wire <= (others => '0');
    [...]
    din => din_wire

    and so on. Also have a signal dout_wire mapped to dout.


    Or try to instantiate the entity as described in the following text of
    the document.


    Hope this helps

    Arnim
    Arnim, Aug 24, 2006
    #4
  5. nfirtaps

    jtw Guest

    Are you including the Xilinx Coregen and/or Unisim libraries in your file
    that instantiates the FIFO?

    JTW
    "Arnim" <> wrote in message
    news:ecl5ln$lcn$-online.net...
    >
    >> This is on the Fuse simulator through ISE. There is a warning that
    >> reads:
    >>
    >> Warning: No entity is bound for inst
    >>
    >> I guess this would be my problem.I do not see a
    >> wrapped_async_fifo.vhd file anywhere but the instance is under my
    >> vhdl module (fpga_fifo_filler) which is named Inst_wrapped_async_fifo
    >> - wrapped_async_fifo. Thanks for pointing me to that warning?
    >> Which I would think should be an error?

    >
    > Yes, this is a very severe warning as it implies that the instance ports
    > are not properly connected to the rest of the design.
    >
    >> Do you have any ideas of what I do to bound this instantiation?

    >
    > It seems to me that the default binding does not work correctly in your
    > case. That's hard to diagnose without sitting in front of your machine.
    > Have a look at
    >
    > http://tams-www.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html#default_binding
    >
    > Especially the paragraph that explains the "set of default binding
    > rules". Basically, you could check whether all of the follwing rules are
    > fulfilled in your design:
    >
    > 1. entity of wrapped_async_fifo is analyzed before architecture
    > of fpga_fifo_filler is analyzed (log file of the compile?)
    > 2. your component declaration for wrapped_async_fifo is identical
    > to the corresponding entity (except formatting)
    > 3. *all* the component ports are actually mapped in the port map to
    > "thingies" of the same type
    >
    > Issue 3 might be violated in your design, as you have an "open" mapped
    > to dout and these "00.."/'0' literals mapped to other ports. I'm not
    > 100% sure about this, but you could try to define signals of exactly the
    > same type as the component ports. Like
    >
    > signal din_wire : std_logic_VECTOR(15 downto 0);
    > [...]
    > din_wire <= (others => '0');
    > [...]
    > din => din_wire
    >
    > and so on. Also have a signal dout_wire mapped to dout.
    >
    >
    > Or try to instantiate the entity as described in the following text of
    > the document.
    >
    >
    > Hope this helps
    >
    > Arnim
    jtw, Aug 25, 2006
    #5
  6. nfirtaps

    nfirtaps Guest

    JTW,
    I have the following lines in my code

    library unisim;
    library unisim.vcomponents.all;

    library xilinxcorelib;

    I have the ISE Simulator Lite, I _think_ this could be because I have
    the lite version.

    Let me briefly recap the following "warnings" I get which prevent me
    from simulating my FIFO Xilinx core.

    warning while synthesizing : Instatiating black box (warning at line
    where I instantiate the core)
    warning while simulating : No entity is bound for inst

    jtw wrote:
    > Are you including the Xilinx Coregen and/or Unisim libraries in your file
    > that instantiates the FIFO?
    >
    > JTW
    > "Arnim" <> wrote in message
    > news:ecl5ln$lcn$-online.net...
    > >
    > >> This is on the Fuse simulator through ISE. There is a warning that
    > >> reads:
    > >>
    > >> Warning: No entity is bound for inst
    > >>
    > >> I guess this would be my problem.I do not see a
    > >> wrapped_async_fifo.vhd file anywhere but the instance is under my
    > >> vhdl module (fpga_fifo_filler) which is named Inst_wrapped_async_fifo
    > >> - wrapped_async_fifo. Thanks for pointing me to that warning?
    > >> Which I would think should be an error?

    > >
    > > Yes, this is a very severe warning as it implies that the instance ports
    > > are not properly connected to the rest of the design.
    > >
    > >> Do you have any ideas of what I do to bound this instantiation?

    > >
    > > It seems to me that the default binding does not work correctly in your
    > > case. That's hard to diagnose without sitting in front of your machine.
    > > Have a look at
    > >
    > > http://tams-www.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html#default_binding
    > >
    > > Especially the paragraph that explains the "set of default binding
    > > rules". Basically, you could check whether all of the follwing rules are
    > > fulfilled in your design:
    > >
    > > 1. entity of wrapped_async_fifo is analyzed before architecture
    > > of fpga_fifo_filler is analyzed (log file of the compile?)
    > > 2. your component declaration for wrapped_async_fifo is identical
    > > to the corresponding entity (except formatting)
    > > 3. *all* the component ports are actually mapped in the port map to
    > > "thingies" of the same type
    > >
    > > Issue 3 might be violated in your design, as you have an "open" mapped
    > > to dout and these "00.."/'0' literals mapped to other ports. I'm not
    > > 100% sure about this, but you could try to define signals of exactly the
    > > same type as the component ports. Like
    > >
    > > signal din_wire : std_logic_VECTOR(15 downto 0);
    > > [...]
    > > din_wire <= (others => '0');
    > > [...]
    > > din => din_wire
    > >
    > > and so on. Also have a signal dout_wire mapped to dout.
    > >
    > >
    > > Or try to instantiate the entity as described in the following text of
    > > the document.
    > >
    > >
    > > Hope this helps
    > >
    > > Arnim
    nfirtaps, Aug 25, 2006
    #6
  7. nfirtaps

    Duth Guest

    Hi,

    It is ideal to open a case with Xilinx Tech Support with this question.
    Here are some things thhat you can look into. Confirm that the output
    netlist created out of coregen in Proj Nav is set to VHDL and not
    verilog. Since ISE Simulator is a mixed language simulator you will not
    get an error about the language. What you can do to confirm this is to
    right click on "view generated HDL file" for the xco file and ensure it
    is VHDL. It defaults to verilog if both synthesis and simulator tools
    are mixed language, i.e XST and ISE Simulator

    Also you do not need to have xilinxcorelib, as long as the wrapper file
    is in the project directory. I suspect the main reason you have unbound
    issue is because of the fact that it is not able to see the VHDL model.

    Also ensure you are using the latest version of ISE as well. With 8.1i
    there were some issues with the coregen flow that have been fully
    addressed in 8.2i.

    Thanks
    Duth
    PS: The lite version does not limit you from simulating any Xilinx
    provided product. The only limtiation is deration when you reach 10,000
    lines of code


    nfirtaps wrote:
    > JTW,
    > I have the following lines in my code
    >
    > library unisim;
    > library unisim.vcomponents.all;
    >
    > library xilinxcorelib;
    >
    > I have the ISE Simulator Lite, I _think_ this could be because I have
    > the lite version.
    >
    > Let me briefly recap the following "warnings" I get which prevent me
    > from simulating my FIFO Xilinx core.
    >
    > warning while synthesizing : Instatiating black box (warning at line
    > where I instantiate the core)
    > warning while simulating : No entity is bound for inst
    >
    > jtw wrote:
    > > Are you including the Xilinx Coregen and/or Unisim libraries in your file
    > > that instantiates the FIFO?
    > >
    > > JTW
    > > "Arnim" <> wrote in message
    > > news:ecl5ln$lcn$-online.net...
    > > >
    > > >> This is on the Fuse simulator through ISE. There is a warning that
    > > >> reads:
    > > >>
    > > >> Warning: No entity is bound for inst
    > > >>
    > > >> I guess this would be my problem.I do not see a
    > > >> wrapped_async_fifo.vhd file anywhere but the instance is under my
    > > >> vhdl module (fpga_fifo_filler) which is named Inst_wrapped_async_fifo
    > > >> - wrapped_async_fifo. Thanks for pointing me to that warning?
    > > >> Which I would think should be an error?
    > > >
    > > > Yes, this is a very severe warning as it implies that the instance ports
    > > > are not properly connected to the rest of the design.
    > > >
    > > >> Do you have any ideas of what I do to bound this instantiation?
    > > >
    > > > It seems to me that the default binding does not work correctly in your
    > > > case. That's hard to diagnose without sitting in front of your machine.
    > > > Have a look at
    > > >
    > > > http://tams-www.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html#default_binding
    > > >
    > > > Especially the paragraph that explains the "set of default binding
    > > > rules". Basically, you could check whether all of the follwing rules are
    > > > fulfilled in your design:
    > > >
    > > > 1. entity of wrapped_async_fifo is analyzed before architecture
    > > > of fpga_fifo_filler is analyzed (log file of the compile?)
    > > > 2. your component declaration for wrapped_async_fifo is identical
    > > > to the corresponding entity (except formatting)
    > > > 3. *all* the component ports are actually mapped in the port map to
    > > > "thingies" of the same type
    > > >
    > > > Issue 3 might be violated in your design, as you have an "open" mapped
    > > > to dout and these "00.."/'0' literals mapped to other ports. I'm not
    > > > 100% sure about this, but you could try to define signals of exactly the
    > > > same type as the component ports. Like
    > > >
    > > > signal din_wire : std_logic_VECTOR(15 downto 0);
    > > > [...]
    > > > din_wire <= (others => '0');
    > > > [...]
    > > > din => din_wire
    > > >
    > > > and so on. Also have a signal dout_wire mapped to dout.
    > > >
    > > >
    > > > Or try to instantiate the entity as described in the following text of
    > > > the document.
    > > >
    > > >
    > > > Hope this helps
    > > >
    > > > Arnim
    Duth, Aug 28, 2006
    #7
  8. nfirtaps

    luke9876

    Joined:
    Jul 5, 2008
    Messages:
    1
    For anybody who googles this..
    I had the same problem with "unbounded blackbox" when I tried to simulate a fifo made in core-gen (I named it myfifo) . I am using Xilinx ISE10.1, and got around the problem by removing my myfifo.xco file and adding the simulation file generated along with the core.
    In Project Navigator-> Sources for: Behavioral Simulation I deleted my fifo.xco and added myfifo.vhd. Core-gen produces the myfifo.ngc (what synthesis uses) and myfifo.vhd (what the simulator will use). Synthesis still gives a warning about 'black box', but it finds the myfifo.ngc component to synthesize with and it simulates now.
    Hope this helps...
    luke9876, Jul 5, 2008
    #8
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