comprehensive documentation for writing testbenches in VHDL

[Marcin Rodzik]

Hello,
I can write simple testbenches using old testbenches written by my
colleagues as a reference telling me how to access test vectors from
files and save results of simulation into another files. It's not a
tough task because it involves usually the same operations. However, I
wonder if there is a COMPREHENSIVE manual/documentation on std.textio
package available anywhere? (with DETAILED description)

I have never found it. Google returns only simple examples of
testbenches. All books on VHDL I know deal with the language itself
and extensions/packages aren't treated thoroughly.

MR

 

[Tricky]

Hello,
I can write simple testbenches using old testbenches written by my
colleagues as a reference telling me how to access test vectors from
files and save results of simulation into another files. It's not a
tough task because it involves usually the same operations. However, I
wonder if there is a COMPREHENSIVE manual/documentation on std.textio
package available anywhere? (with DETAILED description)

I have never found it. Google returns only simple examples of
testbenches. All books on VHDL I know deal with the language itself
and extensions/packages aren't treated thoroughly.

MR

What kind of things would you be looking for? there isnt a lot in
std.textio. Its just a means to get data to/from a text file
std.textio is just a tool for creating more effective testbenches, it
is not a means to an end. By viewing the std.textio source in
modelsim, I see there are only 36 functions/procedures - and most of
these are just variations on a theme of reading/writing text.

If you would like more detailed testbenching theory, I recommend the
book "Writing Testbenches: Functional Verification of HDL models" by
Janick Bergeron. It covers topics like high level modeling and
stimulus and response.

 

[rickman]

What kind of things would you be looking for? there isnt a lot in
std.textio. Its just a means to get data to/from a text file
std.textio is just a tool for creating more effective testbenches, it
is not a means to an end. By viewing the std.textio source in
modelsim, I see there are only 36 functions/procedures - and most of
these are just variations on a theme of reading/writing text.

If you would like more detailed testbenching theory, I recommend the
book "Writing Testbenches: Functional Verification of HDL models" by
Janick Bergeron. It covers topics like high level modeling and
stimulus and response.

I feel his pain. A lot of the libraries aren't described well in most
books. I have learned to use std.textio by trail and error... I mean
tairl and error, I mean trial and error. But I forget between
testbenches and have to teach myself over again. Sometimes I feel
like I am in that movie, "Memento".

Rick

 

[KJ]

But I forget between
testbenches and have to teach myself over again.  Sometimes I feel
like I am in that movie, "Memento".

If you have to teach yourself over again, then ask yourself how hard
can it be to write the body for the following procedures which
probably handle most of the low level file I/O that you'd care
about...

procedure Read_File(File_Name: in STRING; Data: out ptr_arr_t_BYTE;
Length: out integer);
procedure Write_File(File_Name: in STRING; variable Data: in
ptr_arr_t_BYTE; Length: in natural; Write_Status: out BOOLEAN);
procedure Init_Or_Append_File(File_Name: in STRING; Message: in
STRING := ""; File_Mode: in file_open_kind);
procedure Init_File(File_Name: in STRING; Message: in STRING := "");
procedure Read_Text_Line_To_String(variable L: inout Line; variable S:
out STRING);

Then crank it up a notch by writing higher level but more application
domain specific procedures that deal with the types of files that you
regularly work with (For example for image file manipulations, the
following might be useful)

function Read_Tiff_File(File_Name: in STRING) return ptr_t_TIFF_DATA;
procedure Write_Tiff_File(File_Name: in STRING; variable Tiff_Data: in
ptr_t_TIFF_DATA; OK: out BOOLEAN);
impure function Read_Jpeg_File(File_Name: STRING) return BOOLEAN;
impure function Write_Jpeg_File(File_Name: STRING) return BOOLEAN;

Once you have the first set of procedures, you'll likely be able to
forget all about std.textio because you won't be writing any new code
that uses them, they're usage will only be in the 'low level' read and
write files which you've provided a more reasonable user interface to
use.

Of course, for those who think that file I/O to import test vectors is
the way to go (as the OP seem to be suggesting), then the better
advice is to abandon that thinking as soon as possible. Test vector I/
O is far more cumbersome and not nearly as useful or supportable as
actual models simply because the limitations of test vectors then
starts to lead one down the path of (re)inventing test languages
because 'simple' things like loops and handshakes require some
language syntax...which VHDL has. Use it, don't reinvent the square
wheel, use the round one instead.

Kevin Jennings

 

[Marcin Rodzik]

What kind of things would you be looking for? there isnt a lot in
std.textio. Its just a means to get data to/from a text file ...

As I said, I *can* write testbenches... the problem for me is that I
don't always know what is behind the code I copy into new code from
old code. And I like understanding things in deep

If you would like more detailed testbenching theory, I recommend the
book "Writing Testbenches: Functional Verification of HDL models" by
Janick Bergeron. It covers topics like high level modeling and
stimulus and response.

Thank you! I'll try to look for this book.

MR

 

[backhus]

Hello,
I can write simple testbenches using old testbenches written by my
colleagues as a reference telling me how to access test vectors from
files and save results of simulation into another files. It's not a
tough task because it involves usually the same operations. However, I
wonder if there is a COMPREHENSIVE manual/documentation on std.textio
package available anywhere? (with DETAILED description)

I have never found it. Google returns only simple examples of
testbenches. All books on VHDL I know deal with the language itself
and extensions/packages aren't treated thoroughly.

MR

Hi Marcin,
there is a testbench package with documentation and explanations in
opencores.org.
This is the link to it: http://opencores.org/project,vhld_tb

Have a nice simulation
Eilert