Concatenate bits

Discussion in 'VHDL' started by aleksa, Feb 29, 2012.

  1. aleksa

    aleksa Guest

    constant size : integer := 32;
    datain : in std_logic_vector(9 downto 0);
    signal request : std_logic_vector(size-1 downto 0);

    Now I wish to set "request" to "datain", like this:
    request <= "0000000000000000000000" & datain;
    (datain to lower bits, all other bits to zero)

    How do I write that w/o all those zeros?
    It should also work if I later change "size".

    Thanks
    aleksa, Feb 29, 2012
    #1
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  2. aleksa

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    Might try something like,
    Code:
    request <= (size - 1 downto 10 => '0') & datain;
    
    joris, Mar 2, 2012
    #2
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