concatenation problem + difference between mod and rem

Discussion in 'VHDL' started by Mohammed khader, Oct 31, 2004.

  1. Hi all,

    1) Why it is not possible to concatenate two bits to make a vector in
    the following example.

    signal s1,s2 :bit;

    case (s1 & s2 ) is
    WHEN "00" => ...


    end case;

    2) What is the advantage in having two operators(mod and rem ) which
    seems almost similar.Is there any good reason(application) where they
    have specific meaning.

    Thanks in advance.

    Regards,
    Mohammed A.khader.
     
    Mohammed khader, Oct 31, 2004
    #1
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  2. Mohammed  khader

    Alan Fitch Guest

    "Mohammed khader" <> wrote in message
    news:...
    > Hi all,
    >
    > 1) Why it is not possible to concatenate two bits to make a vector

    in
    > the following example.
    >
    > signal s1,s2 :bit;
    >
    > case (s1 & s2 ) is
    > WHEN "00" => ...
    >
    >
    > end case;
    >


    Because the data type is not determinable by the compiler.

    > 2) What is the advantage in having two operators(mod and rem ) which
    > seems almost similar.Is there any good reason(application) where

    they
    > have specific meaning.
    >


    They differ in behaviour for signed values.

    Alan


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    Alan Fitch, Nov 1, 2004
    #2
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