concatenation - VHDL

M

MariuszK

Hello,
--N,K constant and N+3=>K and K>3
signal s1: std_logic_vector(N-1 downto 0);
signal s2: std_logic_vector(K-1 downto 0);

For diffrent N i K I have to write diffrent code
s2<= "0" & s1 & "000";
s2<= "00" & s1 & "000";
s2<= "000" & s1 & "000";
s2<= "0000" & s1 & "000";
etc...

Is it possibility write somethink like this??
s2<= "others=>'0' " & s1 & "000";

Best regards
Mariusz
 
Joined
Mar 10, 2008
Messages
348
Reaction score
0
Hi Marius Z

I believe the best way to do the trick will be an integer;
My idea shown below - hope its useful

Jeppe

signal i: integer;

i <= Conv_integer( s1 & "000");
s2 <= conv_std_logic_vector( i, K-1);
 
M

MariuszK

No, but how about this procedural code:

  s2 <= (others => '0');
  s2(N+2 downto 3) <= s1;

Or, if s1 and s2 are of numeric_std.unsigned type:

  s2 <= resize(s1 & "000", s2'length);

Or, if you are a masochist:

  s2 <= (K-1 downto N+3 => '0') & s1 & "000";

Best of all, write a custom function to do what
you want.  Then you can use for-loops and suchlike
inside the function, but simply call it like this:

  s2 <= insert_shifted(s1, 3, K);

Implementation:

  function insert_shifted
    ( new_data     : std_logic_vector
    ; left_shift   : natural
    ; result_width : positive
    ) return std_logic_vector is
    variable result: std_logic_vector(result_width-1 downto 0);
    constant d_width: natural := new_data'length;
  begin
    assert result_width >= d_width + left_shift
      report "output (" & integer'image(result_width)
           & " bits) is too narrow for new_data ("
           & integer'image(d_width)
           & " bits) left-shifted by " & integer'image(left_shift)
      severity error;
    result := (others => '0');
    result(d_width + left_shift - 1 downto left_shift) := new_data;
    return result;
  end;

Conclusion:
  ALWAYS consider a function for bit-manipulation problems.
  It pays you back handsomely.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Jim, Jonathan,
Thank you!

Jonathan,
Thank you once again for very good conclusion - "ALWAYS consider a
function..."

I was teached VHDL by persons which had next rules:
- do not use function - functions create unnecessary logic compare to
the same inline code
- do not use variables - variables create additional logic compare to
signals
etc...

Now, I am know that it is not true ... but sometimes still programing
like "masochist".

Best regards,
Mariusz
 
Joined
Feb 25, 2010
Messages
38
Reaction score
0
general uses of concatenation operator is explained here/..
vhdlguru.blogspot.com/2010/03/concatenation-operator-in-vhdl.html
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Members online

No members online now.

Forum statistics

Threads
473,744
Messages
2,569,483
Members
44,903
Latest member
orderPeak8CBDGummies

Latest Threads

Top