Concurrent assignment Modelsim problem. Please, need help ASAP.

Discussion in 'VHDL' started by jason12, Jul 29, 2007.

  1. jason12

    jason12

    Joined:
    Jul 29, 2007
    Messages:
    1
    Hi,

    I am trying to use someone else code and having issues in modelsim.

    Here it is.

    signal abc : std_logic_vector(10 downto 0);
    ......

    abc(10 downto 9) <= "00";
    abc(8 downto 0) <= "111111111";


    After compilation and simulation the VCD file contains abc(10) and abc(8) only.

    If I change it to
    abc(10 downto 0) <= "00111111111";
    Modelsim is happy and VCD has full vector.


    The problem is that the original code is more complicated than the one shown as an example. Plus I am not at liberty to change it (not mine). Is there a way to force Modelsim to compile/simulate the original assignments right?

    Thanks
     
    jason12, Jul 29, 2007
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Chad A. Beckner
    Replies:
    2
    Views:
    578
    Chad A. Beckner
    Jun 18, 2004
  2. IC Browsers
    Replies:
    1
    Views:
    350
    Roedy Green
    May 10, 2004
  3. kaji
    Replies:
    1
    Views:
    635
    quantum_dot
    Mar 15, 2007
  4. John Coffey
    Replies:
    1
    Views:
    135
    kapilp
    Mar 29, 2006
  5. Sparticus
    Replies:
    10
    Views:
    142
    J├╝rgen Exner
    Mar 10, 2006
Loading...

Share This Page