concurrent signal assignment in a process

Discussion in 'VHDL' started by alb, Aug 27, 2013.

  1. alb

    alb Guest

    Hi everyone,

    I generally use the vcom to analyze and build libraries and units for
    presynth simulation and only after I'm happy with it I proceed with
    synthesis. Yesterday, though, I tried to compile the following code [1]
    with synplify_pro without success (while vcom happily went through):

    > architecture tfsm_arch of tfsm is
    > -- Note: No signal declarations.
    > begin -- tfsm_arch
    >
    > main : process (CLK, RST) is
    > -- control wires
    > subtype ctr_t is std_ulogic;
    > variable nrd_v : ctr_t;
    > variable nwr_v : ctr_t;
    > variable auto : boolean;
    > -------------------------------------------------------------------------------
    > procedure update_ports is
    > begin -- purpose: synthesize a wire from the register to the port
    > nRD_o <= nrd_v when auto = true else nrd_i; -- ***Synplify Pro AE Error
    > nWR_o <= nwr_v when auto = true else nwr_i;
    > add_o <= add_v when auto = true else add_i;
    >
    > end procedure update_ports;
    > -------------------------------------------------------------------------------
    > -- some more procedures here...
    > -------------------------------------------------------------------------------
    > begin -- process main
    > case template_g is
    > when a_rst => template_a_rst;
    > when s_rst => template_s_rst;
    > when so_rst => template_so_rst;
    > when others => template_v_rst;
    > end case;
    > end process main;


    Synplify Pro AE (integrated in LiberoSoC) barf something like this:

    @E: CD242
    :"/home/pol/polar_svn/firmware/obox/frontend_alb/firmware/hdl/tfsm.vhd":116:21:116:24|Expecting
    ;
    @E: CD204
    :"/home/pol/polar_svn/firmware/obox/frontend_alb/firmware/hdl/tfsm.vhd":116:21:116:24|Expecting
    sequential statement

    Being the procedure defined in a process I may understand why it
    'expects a sequential statement', but is this something related to
    synthesis only?
    Why vcom does not complain?
    It looks like I cannot have a concurrent signal assignment in a process
    (which makes sense since signal assignment is 'scheduled').

    Moreover I'm quite confused when it comes to the various steps involved
    in synthesis. It seems the tool is failing during 'parsing' which is
    something I expected to be part of the 'analysis', therefore equivalent
    to the 'vcom' result.

    Anyway I changed the conditional signal assignment statement with a
    sequential one (if/then/else) and everything works fine. Still I'd
    appreciate if someone can enlighten me on this topic.

    Al

    [1] some of you may have recognized Mike Treseler's template.

    --
    A: Because it fouls the order in which people normally read text.
    Q: Why is top-posting such a bad thing?
    A: Top-posting.
    Q: What is the most annoying thing on usenet and in e-mail?
    alb, Aug 27, 2013
    #1
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  2. alb

    Andy Guest

    Al,

    Turn on the 2008 VHDL option in Synplify Pro.

    BTW, those are not "concurrent assignment statements in a process". They are "conditional assignment statements" (LRM 10.5.3), which, under 2008 are also allowed in sequential (process/subprogram) regions, as are selected assignment statements. In a sequential statement region, these can also be variable assignments.

    However, they are statements, and do NOT create a new form of conditional/selected expression, and are therefore not usable as, say, an initializer ona constant/signal/variable declaration.

    Andy
    Andy, Aug 27, 2013
    #2
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  3. alb

    alb Guest

    On 27/08/2013 16:09, Andy wrote:
    []
    > Turn on the 2008 VHDL option in Synplify Pro.


    Uhm, apparently the 2008 VHDL switch is on...

    >
    > BTW, those are not "concurrent assignment statements in a process".
    > They are "conditional assignment statements" (LRM 10.5.3), which,
    > under 2008 are also allowed in sequential (process/subprogram)
    > regions, as are selected assignment statements. In a sequential
    > statement region, these can also be variable assignments.


    crap I mixed them: I should have said 'conditional signal assignment
    statement' which used to be a 'concurrent statement' (LRM IEEE1076-1993
    9.5.1).

    > However, they are statements, and do NOT create a new form of
    > conditional/selected expression, and are therefore not usable as,
    > say, an initializer on a constant/signal/variable declaration.


    I'm puzzled now. Do you mean that I cannot use this statement to infer a
    logic which allows me to 'select' one of two constant/signal/variable
    and assign it to another variable/signal? (like a multiplexer)
    alb, Aug 27, 2013
    #3
  4. alb

    Andy Guest

    Al,

    Oops,

    As of June 2012 the Synplify Reference manual did not list sequential conditional/selected assignments as being a 2008 feature that is supported yet.

    If you want it, let them know! That's the only way they know what is important to their users. If enough of us let them know these features that we want supported, they will support them.


    WRT expressions, what I meant is you CANNOT do something like the following:

    constant foo_flag : std_logic := '1' when foo = 0 else '0';

    Conditional/selected assignment statements are their own kind of statement, not a new kind of expression that can be used anywhere an expression can be used.

    Andy
    Andy, Aug 27, 2013
    #4
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