Concurrent vs Sequential

[VHDL_newb]

Hi,

Can some one give me a breakdown of the advantages and disdvantages of using concurrent and sequential statements in VHDL design?

Thanks

 

[jeppe]

Hi
A quick and short answer:

Concurrent will mostly be used for combinatorial logic (my opinion)
Sequential statements can however be used for combinatorial logic as well.
Specially in combination with variables will it be possible to write sequential VHDL code which implements an algorithm etc.
In combination with a Rising_edge( clk) statement will you be able to define circuit with F/F's -> Sequential logic.

Hope you got the meaning.
Try to download Evita VHDL (an interactive book on the topic)

Your welcome
Jeppe