"condition in IF generate must be static"

Discussion in 'VHDL' started by qwerty321, Dec 12, 2009.

  1. qwerty321

    qwerty321

    Joined:
    Dec 9, 2009
    Messages:
    18
    How can i solve the problem of:
    "condition in IF generate must be static"

    thank you
    qwerty321, Dec 12, 2009
    #1
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