conditional architecture

Discussion in 'VHDL' started by valentin tihomirov, Sep 28, 2004.

  1. I'm sure this is currently not possible. What are the future prospects or
    any better solution?


    u1: entity E (<cond> ? ARCH_A : ARCH_B)
    map ports (...);


    I don't like conditional generates nor configurations as they are
    troublesome.
    valentin tihomirov, Sep 28, 2004
    #1
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