Conditional assignment to signals

[Johnsy Joseph]

Hello Everybody,

I would be grateful if somebody helped with this. The problem I am
facing is how to control an assignement to signal based on the changes
that happen to a variable declared in a process block. The situation
is like this.

architecture circuit of queue is
begin

signal queueisfull: std_logic;

queueisfull <= 1 when queuetop = '100' else '0';

process(clk)
variable queuetop: std_logic;
begin

-- I have a large number of statements that assign to queuetop at
different
-- places. Anytime "queuetop" changes I want the "queueisfull"
signal to get
-- the appropriate value but queuetop is defined in the process
only.

end process;
end circuit;

Do I have something like a global variable?

Please forgive me if the question is stupid. I am new to VHDL and
hence the confusion.
Thanks for the help
Warm Regards
Johnsy

 

[mike_treseler]

Just put the signal assignment

queueisfull <= 1 when queuetop = '100' else '0';

inside your process.

-- Mike Treseler

 

[Srinivasan Venkataramanan]

Hi,

Hello Everybody,

I would be grateful if somebody helped with this. The problem I am
facing is how to control an assignement to signal based on the changes
that happen to a variable declared in a process block. The situation
is like this.

Simplest solution would be to have the queutop declared as a signal - is
that too difficult in your case?

A straight forward fix to your problem may be to try using "shared
variables", but I remember reading in this group a few years back that
shared variables don't have "memory" to remmeber events, so I am not too
sure whether you concurrent "when..else" will get triggerred due to a change
in a shared variable.

BTW - you will need VHDL-93 to use shared var.

architecture circuit of queue is
begin

signal queueisfull: std_logic;

queueisfull <= 1 when queuetop = '100' else '0';

^^^^^^ Shouldn't this
be double-quotes?

HTH
Srinivasan
http://www.noveldv.com

--
Srinivasan Venkataramanan
Corp. Appl. Engineer
Synopsys India Pvt. Ltd.
Bangalore, India
email:synopsys.com@svenkat
I own my words and not my employer, unless specifically mentioned

 

[Srinivasan Venkataramanan]

Hi,

Just put the signal assignment

queueisfull <= 1 when queuetop = '100' else '0';

inside your process.

Isn't when..else a concurrent statement?

-- Mike Treseler

P.S. Not sure if this is the same Mike Tressler as:
(e-mail address removed) ?
--
Srinivasan Venkataramanan
Corp. Appl. Engineer
Synopsys India Pvt. Ltd.
Bangalore, India
email:synopsys.com@svenkat
I own my words and not my employer, unless specifically mentioned

 

[Jim Lewis]

Isn't when..else a concurrent statement?

At least until the next language revision.
There is a proposal to address this.
See FT10B at:
http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/proposals.html

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Mike Treseler]

Isn't when..else a concurrent statement?

You're right, better make that:
"Just put a signal assignment inside your process."

-- Mike Treseler

 

[Mohammed A.khader]

architecture circuit of queue is
begin

signal queueisfull: std_logic;

queueisfull <= 1 when queuetop = '100' else '0';

process(clk)
variable queuetop: std_logic;
begin

-- I have a large number of statements that assign to queuetop at
different
-- places. Anytime "queuetop" changes I want the "queueisfull"
signal to get
-- the appropriate value but queuetop is defined in the process
only.

end process;
end circuit;

Hi,

signal queuetop (in concurrent statement) should be of
integer/natural type.Preferably natural because its function is to
count the number of elements in the queue(So Its value can only be in
the range of 0 TO MAX_LENGTH).

In your code the scope of the queuetop is only inside the process
hence you should declare in the ARCHITECTURE declaration part.

According to me your code should be something like this....

ARCHITECTURE circuit OF queue IS

signal queueisfull: std_logic;
SIGNAL queuetop : natural;
BEGIN


queueisfull <= '1' when queuetop = 100 else '0';

PROCESS(clk)
--So decalare a new variable called process_queuetop
VARIABLE process_queuetop: natural;
BEGIN

-- do what ever assignment you want to do here for variable
process_queuetop
-- assign the value of VARIABLE process_queuetop to the SIGNAL
queuetop as shown below.
-- This will trigger the concurrent statement.
queuetop <= process_queuetop;
END PROCESS;
END ARCHITECTURE circuit;

 

[rickman]

You're right, better make that:
"Just put a signal assignment inside your process."

-- Mike Treseler

It doesn't matter. Moving the assignment of queueisfull inside the
clocked process will make it a registered signal which is not what the
OP seems to intend. But from the several mistakes he has made, I think
he might not be sure of what he intended.

My guess is that he is learning the language. In that case I think he
is taking the wrong approach. I encourage people to always design in
terms of hardware, thinking of how they expect to implement the design
in logic and register blocks, *then* try to describe this logic using
the HDL. Typically this produces very consistent code that is easier to
understand and debug.

--

Rick "rickman" Collins

(e-mail address removed)
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
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[Raghavendra]

HI,
Shared variable are not inferred as hardware.Better to declare
queuetop as signal.

Regards,
Raghavendra.S