Conditional Assignments in Constants

Discussion in 'VHDL' started by kevin.neilson@xilinx.com, Mar 20, 2013.

  1. Guest

    Did VHDL-2008 ever add a way to do this?

    constant k : integer := 5 when BOOLEAN_GENERIC else 8;

    I.e, to do the Verilog ?: operator? Having to write a function to make this work is awkward and verbose.
    , Mar 20, 2013
    #1
    1. Advertising

  2. KJ Guest

    On Wednesday, March 20, 2013 4:39:06 PM UTC-4, wrote:
    > Did VHDL-2008 ever add a way to do this?
    > constant k : integer := 5 when BOOLEAN_GENERIC else 8;
    > I.e, to do the Verilog ?: operator? Having to write a function to
    > make this work is awkward and verbose.


    The awkward and verbose function is at the end of the post. However, once you've taken the trouble to write (or copy/paste) this code, you should putit into a package of 'useful, general purpose functions that you can then use whenever you need them' and you can use those functions without ever having to look at that code again.

    Effectively, you extended the language in your own preferred direction and there is nothing negative about that. You won't even need to wonder if some version of the language now supports what you want or, just as importantly, wonder if the tool you're using supports that new construct. Plus, whatif down the road, you'd like to have a function that works with std_logic conditions (or input parameters), you can simply copy/paste the code, modify two lines and be ready to go thanks to VHDL's function overloading. The ability to basically customize the language is a 'good thing', waiting for the standards folks and the tool supplier folks to get onboard...not so mucah a 'good thing'.

    Using the code that you'll write once and then (probably) never have to look at again is as simple as using any std_logic or numeric_std or other library function that you already take for granted. Now you'll have the start of your own library of functions that you can also take for granted.

    library work.my_pkg_of_vhdl_stuff.all;
    ....
    constant k: integer := sel(BOOLEAN_GENERIC, 5, 8);
    or ...
    constant k: integer := sel(Cond => BOOLEAN_GENERIC, If_True => 5, If_False => 8);

    Kevin Jennings

    ---*** START CODE ***---
    ----------------------------------------------------------------
    -- Functions to select one or the other based on a boolean (or
    -- std_ulogic or std_logic) input.
    -- Analogous to the C statement x = Cond ? a : b
    ----------------------------------------------------------------
    function sel(Cond: BOOLEAN; If_True, If_False: integer) return integer is
    begin
    if (Cond = TRUE) then
    return(If_True);
    else
    return(If_False);
    end if;
    end function sel;
    ---*** END CODE ***---
    KJ, Mar 20, 2013
    #2
    1. Advertising

  3. Andy Guest

    VHDL-2008 allows conditional and selected assignments to variables or signals in sequential statements, but not in the initialization of a declaration.

    It would be nice to be able to use a conditional assignment in an initialization.

    I'm assuming that this boolean generic controls several things, otherwise you could just pass in the value of K as a generic instead.

    Try the following, slightly less "awkward and verbose" method:

    type switch_t is array (boolean) of integer;
    constant switch : switch_t := (true => 5, false => 8);
    constant k : integer := switch(boolean_generic);

    Andy
    Andy, Mar 21, 2013
    #3
  4. Guest

    That's a good function. I can use that. I would prefer it, though, if very basic things were built into the language. If I'm reading somebody else's code I shouldn't have to find that package that 'sel' is defined in just because the language doesn't have a ?: built in. From what I can tell, I can't even convert a Boolean into an integer unless I write my own function.
    , Mar 21, 2013
    #4
  5. Guest

    That's a good one too. It's nice to have something simple that's close to where I'm using it which may be clearer than if it's off in a package somewhere.
    , Mar 21, 2013
    #5
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Neil Zanella
    Replies:
    2
    Views:
    974
    Neil Zanella
    Oct 26, 2003
  2. Nicolas Matringe
    Replies:
    9
    Views:
    713
    Mike Treseler
    Jun 14, 2004
  3. Gary Thorpe

    Using aggregates for assignments

    Gary Thorpe, Jun 14, 2004, in forum: VHDL
    Replies:
    4
    Views:
    687
  4. ALuPin

    Back-Annotate Assignments

    ALuPin, Oct 20, 2004, in forum: VHDL
    Replies:
    1
    Views:
    1,769
    Ben Twijnstra
    Oct 20, 2004
  5. Alec S.
    Replies:
    10
    Views:
    10,083
    Alec S.
    Apr 16, 2005
Loading...

Share This Page