Conditional compile in VHDL

Discussion in 'VHDL' started by Dave Miller, Jan 30, 2005.

  1. Dave Miller

    Dave Miller Guest

    Hello all --

    I have seen several posts with questions regarding techniques for
    conditional compiles. I have a similar question, but I don't want to
    conditionally generate hardware or multiple configurations. I just want to
    have multiple sets of constants in my package, and select a set depending on
    whether I am running a simulation, or compiling hardware. For example
    (using C preprocessor directives)

    #ifdef simulation

    constant PixelsPerLine : integer := 32;
    constant LinesPerFrame : integer := 16;

    #else

    constant PixelsPerLine : integer := 1024
    constant LinesPerFrame : integer := 512;

    #endif

    This way I can just define "simulation" in my testbench, and I don't have to
    modify my package definitions depending on what I am doing. I have seen
    suggestion that I just use a C preprocessor, but I sure would like to do it
    all in VHDL so I can stay within my Xilinx environment. Is there any way to
    do this?

    Thanks in advance

    Dave Miller
    Tecolote Development
     
    Dave Miller, Jan 30, 2005
    #1
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  2. Dave Miller

    David Bishop Guest

    A "partial solution" to this problem is the package generics proposal:
    http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/dta_type_genericity.pdf
    Take a look at:
    http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/proposals.html
    for a list of all of the proposals we have to update the language.

    Dave Miller wrote:

    > Hello all --
    >
    > I have seen several posts with questions regarding techniques for
    > conditional compiles. I have a similar question, but I don't want to
    > conditionally generate hardware or multiple configurations. I just want to
    > have multiple sets of constants in my package, and select a set depending on
    > whether I am running a simulation, or compiling hardware. For example
    > (using C preprocessor directives)
    >
    > #ifdef simulation
    >
    > constant PixelsPerLine : integer := 32;
    > constant LinesPerFrame : integer := 16;
    >
    > #else
    >
    > constant PixelsPerLine : integer := 1024
    > constant LinesPerFrame : integer := 512;
    >
    > #endif
    >
    > This way I can just define "simulation" in my testbench, and I don't have to
    > modify my package definitions depending on what I am doing. I have seen
    > suggestion that I just use a C preprocessor, but I sure would like to do it
    > all in VHDL so I can stay within my Xilinx environment. Is there any way to
    > do this?
    >
    > Thanks in advance
    >
    > Dave Miller
    > Tecolote Development
    >
    >
    >
    >
     
    David Bishop, Jan 30, 2005
    #2
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  3. Dave Miller wrote:

    > I have seen several posts with questions regarding techniques for
    > conditional compiles. I have a similar question, but I don't want to
    > conditionally generate hardware or multiple configurations. I just want to
    > have multiple sets of constants in my package, and select a set depending on
    > whether I am running a simulation, or compiling hardware.


    Consider some sort of constant data structure.

    -- Mike Treseler
    ----------------------------------------------
    package display is
    type display_enum_t is (small, medium, large);
    type display_spec_t is
    record
    PixelsPerLine : positive;
    LinesPerFrame : positive;
    end record display_spec_t;

    type displays_t is array (display_enum_t) of display_spec_t;

    constant example_spec : display_spec_t :=
    (PixelsPerLine => 32,
    LinesPerFrame => 16);

    constant bag_o_specs :
    displays_t := (
    small => (
    PixelsPerLine => 32,
    LinesPerFrame => 16
    ),
    medium => (
    PixelsPerLine => 64,
    LinesPerFrame => 32
    ),
    large => (
    PixelsPerLine => 1024,
    LinesPerFrame => 512
    )
    );

    constant test_this_line : positive := bag(large).PixelsPerLine;

    end package display;
     
    Mike Treseler, Jan 30, 2005
    #3
  4. Mike Treseler wrote:

    > constant test_this_line : positive := bag(large).PixelsPerLine;


    constant test_this_line : positive := bag_o_specs(large).PixelsPerLine;

    is what I meant.
    Doooh!

    -- Mike Treseler
     
    Mike Treseler, Jan 30, 2005
    #4
  5. Dave Miller a écrit :
    > Hello all --
    >
    > I have seen several posts with questions regarding techniques for
    > conditional compiles. I have a similar question, but I don't want to
    > conditionally generate hardware or multiple configurations. I just want to
    > have multiple sets of constants in my package, and select a set depending on
    > whether I am running a simulation, or compiling hardware. For example
    > (using C preprocessor directives)
    >
    > #ifdef simulation
    >
    > constant PixelsPerLine : integer := 32;
    > constant LinesPerFrame : integer := 16;
    >
    > #else
    >
    > constant PixelsPerLine : integer := 1024
    > constant LinesPerFrame : integer := 512;
    >
    > #endif
    >
    > This way I can just define "simulation" in my testbench, and I don't have to
    > modify my package definitions depending on what I am doing. I have seen
    > suggestion that I just use a C preprocessor, but I sure would like to do it
    > all in VHDL so I can stay within my Xilinx environment. Is there any way to
    > do this?


    Hello
    What I usually do (but I don't define my constants in a package) is use
    generic parameters with default values at the top level and override
    them in the testbench for simulation.
    The only drawback is for gate-level simulation because the generated
    VHDL entity doesn't have generics anymore.

    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide
    | | | | | (_| |_| | Invalid return address
    |_| |_|_|\__|\___/
     
    Nicolas Matringe, Feb 1, 2005
    #5
  6. Hi Dave,

    even you do not prefer the C preprocessor-solution, you might check my EVHDL
    at www.entner-electronics.com , in the download-section.

    Regards,

    Thomas

    "Dave Miller" <> schrieb im Newsbeitrag
    news:...
    >
    > Hello all --
    >
    > I have seen several posts with questions regarding techniques for
    > conditional compiles. I have a similar question, but I don't want to
    > conditionally generate hardware or multiple configurations. I just want
    > to have multiple sets of constants in my package, and select a set
    > depending on whether I am running a simulation, or compiling hardware.
    > For example (using C preprocessor directives)
    >
    > #ifdef simulation
    >
    > constant PixelsPerLine : integer := 32;
    > constant LinesPerFrame : integer := 16;
    >
    > #else
    >
    > constant PixelsPerLine : integer := 1024
    > constant LinesPerFrame : integer := 512;
    >
    > #endif
    >
    > This way I can just define "simulation" in my testbench, and I don't have
    > to modify my package definitions depending on what I am doing. I have
    > seen suggestion that I just use a C preprocessor, but I sure would like to
    > do it all in VHDL so I can stay within my Xilinx environment. Is there
    > any way to do this?
    >
    > Thanks in advance
    >
    > Dave Miller
    > Tecolote Development
    >
    >
    >
    >
    >
     
    Thomas Entner, Feb 9, 2005
    #6
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