Conditional declarations

Discussion in 'VHDL' started by Colin Beighley, Jul 20, 2011.

  1. Hello,

    I keep running across situations where a conditional variable or
    signal declaration would be very useful in simulation (for instance,
    declaring full range integers or reals), but I don't want any of these
    to attempt to be synthesized. Is there an eloquent way of doing this?
    I don't believe you can use the generate statement for declarations. I
    have heard of people using the C preprocessor for this, but this seems
    like a hack IMO.

    Colin
     
    Colin Beighley, Jul 20, 2011
    #1
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  2. On Jul 20, 11:14 am, Colin Beighley <> wrote:
    > Hello,
    >
    > I keep running across situations where a conditional variable or
    > signal declaration would be very useful in simulation (for instance,
    > declaring full range integers or reals), but I don't want any of these
    > to attempt to be synthesized. Is there an eloquent way of doing this?
    > I don't believe you can use the generate statement for declarations. I
    > have heard of people using the C preprocessor for this, but this seems
    > like a hack IMO.
    >
    > Colin


    Okay so I had a brain fart and forgot about --synthesis translate_off.
    I've also looked into the archives and seen that it doesn't seem to be
    supported for synthesis, though, except for within conditional
    generate statements.
     
    Colin Beighley, Jul 20, 2011
    #2
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  3. Colin Beighley

    KJ Guest

    On Jul 20, 2:14 pm, Colin Beighley <> wrote:
    > Hello,
    >
    > I keep running across situations where a conditional variable or
    > signal declaration would be very useful in simulation (for instance,
    > declaring full range integers or reals), but I don't want any of these
    > to attempt to be synthesized. Is there an eloquent way of doing this?
    > I don't believe you can use the generate statement for declarations. I
    > have heard of people using the C preprocessor for this, but this seems
    > like a hack IMO.
    >


    You can declare signals within a generate statement. Then set the
    generate condition appropriately to not generate for synthesis.

    if xxx generate
    signal xyz_real: real;
    begin
    xyz <= to_real(xyz_fp);
    end generate xxx;

    Kevin Jennings
     
    KJ, Jul 20, 2011
    #3
  4. On Jul 20, 2:03 pm, KJ <> wrote:
    > On Jul 20, 2:14 pm, Colin Beighley <> wrote:
    >
    > > Hello,

    >
    > > I keep running across situations where a conditional variable or
    > > signal declaration would be very useful in simulation (for instance,
    > > declaring full range integers or reals), but I don't want any of these
    > > to attempt to be synthesized. Is there an eloquent way of doing this?
    > > I don't believe you can use the generate statement for declarations. I
    > > have heard of people using the C preprocessor for this, but this seems
    > > like a hack IMO.

    >
    > You can declare signals within a generate statement.  Then set the
    > generate condition appropriately to not generate for synthesis.
    >
    > if xxx generate
    >    signal xyz_real:  real;
    > begin
    >    xyz <= to_real(xyz_fp);
    > end generate xxx;
    >
    > Kevin Jennings


    So I think the --synthesis translate_off/on statements will give me
    the functionality I need for simulation vs synthesis, but a
    conditional declaration of the #ifdef type would still be useful.
    Signals declared in generate statements are limited in scope to their
    generate statement, correct?
     
    Colin Beighley, Jul 21, 2011
    #4
  5. Colin Beighley

    KJ Guest

    On Jul 21, 12:13 pm, Colin Beighley <> wrote:
    > On Jul 20, 2:03 pm, KJ <> wrote:
    >
    >
    >
    >
    >
    > > On Jul 20, 2:14 pm, Colin Beighley <> wrote:

    >
    > > > Hello,

    >
    > > > I keep running across situations where a conditional variable or
    > > > signal declaration would be very useful in simulation (for instance,
    > > > declaring full range integers or reals), but I don't want any of these
    > > > to attempt to be synthesized. Is there an eloquent way of doing this?
    > > > I don't believe you can use the generate statement for declarations. I
    > > > have heard of people using the C preprocessor for this, but this seems
    > > > like a hack IMO.

    >
    > > You can declare signals within a generate statement.  Then set the
    > > generate condition appropriately to not generate for synthesis.

    >
    > > if xxx generate
    > >    signal xyz_real:  real;
    > > begin
    > >    xyz <= to_real(xyz_fp);
    > > end generate xxx;

    >
    > > Kevin Jennings

    >
    > So I think the --synthesis translate_off/on statements will give me
    > the functionality I need for simulation vs synthesis, but a
    > conditional declaration of the #ifdef type would still be useful.
    > Signals declared in generate statements are limited in scope to their
    > generate statement, correct?- Hide quoted text -
    >


    Yes, the signals are limited in scope to being within the generate
    statement. But that doesn't mean that they can't access things that
    are outside of scope.

    You asked for a conditional method to declare signals (and presumably
    use them) for simulation but not synthesis. That's precisely what the
    language itself can provide you with the generate statement. The
    translate_off/on has some limitations:
    - translate_off/on is not conditional 'as-is' (which would seem to
    violate what you said you were looking for). People do play games
    with how they write the text to accomplish their specific goals, but
    it is always kludgy
    - translate_off/on is a pragma that is embedded within a comment...so
    it rightfully gets ignored by other tools. This implies that your
    simulations will compile and run just fine, only when you run the
    synthesis tool do you find that you have an 'off' without an 'on' or
    typed 'translate off' or 'translate on' or some other simple
    misspelling. They don't necessarily take long to clean up and fix,
    but why bother when the generate statement is accepted by all tools
    since it is part of the language and does what it appears that you
    need? If it doesn't perhaps you should explain a bit more about how
    the example I gave you doesn't meet your needs and we can go from
    there.

    About the only limitation of the generate statement I can think of is
    that it is only applicable inside the architecture of an entity. In
    particular it cannot be used in code that is in a package. There you
    would have to use translate_off/on.

    Kevin Jennings
     
    KJ, Jul 21, 2011
    #5
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