conditional model generation

Discussion in 'VHDL' started by Holger Venus, Jun 25, 2004.

  1. Holger Venus

    Holger Venus Guest

    Hi to all,



    Does some body have an idea how to generate a model based on

    generic control, both for the architecture part (component instantiation

    and conditional generated wiring) and the entity ports!! as well?

    I am trying to create a generic model with a scalable hardware (via

    generate statement in the architecture part). Depending on the

    generated architecture, the port declaration has to be adapted as well!!

    I do not know a way to use generate statements in the entity section

    directly. Could there be a trick to use a record structure in the entity

    but declare the record in an external package?

    Is it possible to use the generate statement in a package declaration

    section? What about block statement usage in the package section?



    Thank you for your help



    Holger
     
    Holger Venus, Jun 25, 2004
    #1
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  2. One approach is to make your inputs and outputs vectors. Use a generic
    to indicate how many of each your architecture needs. Use can use an
    alias to map the vector components to "symbolic" names if this can be
    done programmatically.

    Hope this helps!

    Drew

    In article <>,
    "Holger Venus" <> wrote:

    > Hi to all,
    >
    >
    >
    > Does some body have an idea how to generate a model based on
    >
    > generic control, both for the architecture part (component instantiation
    >
    > and conditional generated wiring) and the entity ports!! as well?
    >
    > I am trying to create a generic model with a scalable hardware (via
    >
    > generate statement in the architecture part). Depending on the
    >
    > generated architecture, the port declaration has to be adapted as well!!
    >
    > I do not know a way to use generate statements in the entity section
    >
    > directly. Could there be a trick to use a record structure in the entity
    >
    > but declare the record in an external package?
    >
    > Is it possible to use the generate statement in a package declaration
    >
    > section? What about block statement usage in the package section?
    >
    >
    >
    > Thank you for your help
    >
    >
    >
    > Holger
     
    Andrew Reynolds, Dec 31, 2004
    #2
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