configurations and generics

Discussion in 'VHDL' started by Andy Luotto, Sep 10, 2008.

  1. Andy Luotto

    Andy Luotto Guest

    I am designing a verification environment with parameters, e.g.

    entity cordic_tb is
    generic(
    pipe : integer;
    datawidth : integer;
    anglewidth : integer
    );
    end cordic_tb;
    architecture beh of cordic_tb is ...

    and i would like to design configurations of the same test bench with
    different generics, something like

    configuration c_cordic_v7_nom of cordic_tb is
    for beh
    -- generic map(
    -- pipe => 5
    -- datawidth =>11
    -- anglewidth =>16
    -- );

    for i_cordic: cordic
    use configuration bblocks_lib.cordic_v7_configuration;
    end for;
    .....

    can i place the generic map (clike that ommented out) to control the
    generics of the top (and not just the sub modules generics)?

    i know i can pass those parameters as simulator arguments (e.g. ncelab
    anglewidth=16 ...), still i'd like to handle this in the HDL to make
    simualtor independent

    thanks
     
    Andy Luotto, Sep 10, 2008
    #1
    1. Advertising

  2. Andy Luotto

    Andy Guest

    On Sep 10, 9:45 am, Andy Luotto <> wrote:
    > I am designing a verification environment with parameters, e.g.
    >
    > entity cordic_tb is
    >   generic(
    >     pipe  : integer;
    >     datawidth  : integer;
    >     anglewidth : integer
    >   );
    > end cordic_tb;
    > architecture beh of cordic_tb is ...
    >
    > and i would like to design configurations of the same test bench with
    > different generics, something like
    >
    > configuration c_cordic_v7_nom of cordic_tb is
    >   for beh
    > --  generic map(
    > --    pipe  => 5
    > --    datawidth  =>11
    > --    anglewidth =>16
    > --  );
    >
    >     for i_cordic: cordic
    >       use configuration bblocks_lib.cordic_v7_configuration;
    >     end for;
    > ....
    >
    > can i place the generic map (clike that ommented out) to control the
    > generics of the top (and not just the sub modules generics)?
    >
    > i know i can pass those parameters as simulator arguments (e.g. ncelab
    > anglewidth=16 ...), still i'd like to handle this in the HDL to make
    > simualtor independent
    >
    > thanks


    I think you may have to have a top level wrapper over the tb to do
    that. But I don't use configurations much anymore, preferring to use
    generics and entity instantiations. If you really want tool
    independence, you can create a top level wrapper for each would-be
    configuration that sets the generics for you.

    Andy
     
    Andy, Sep 10, 2008
    #2
    1. Advertising

  3. Andy Luotto wrote:

    > and i would like to design configurations of the same test bench with
    > different generics, something like


    I know this isn't any help, but good luck with that! I struggled with
    getting configurations to do anything *useful* (in a concise manner) for
    me and gave up after a couple of days... :(

    Regards,

    --
    Mark McDougall, Engineer
    Virtual Logic Pty Ltd, <http://www.vl.com.au>
    21-25 King St, Rockdale, 2216
    Ph: +612-9599-3255 Fax: +612-9599-3266
     
    Mark McDougall, Sep 11, 2008
    #3
  4. Andy Luotto

    Andy Luotto Guest

    >
    > I know this isn't any help, but good luck with that! I struggled with
    > getting configurations to do anything *useful* (in a concise manner) for
    > me and gave up after a couple of days... :(
    >
    > Regards,
    >



    on my side i can say i was *forced* by my customer to use vhdl, since
    i largely prefers (system) verilog: half the time to do the same
    stuff ... i tried to use vhdl in a concise manner which is competitive
    with verlog with no success ;-)
     
    Andy Luotto, Sep 11, 2008
    #4
  5. Andy Luotto

    Andy Guest

    On Sep 11, 2:17 am, Andy Luotto <> wrote:
    > > I know this isn't any help, but good luck with that! I struggled with
    > > getting configurations to do anything *useful* (in a concise manner) for
    > > me and gave up after a couple of days... :(

    >
    > > Regards,

    >
    > on my side i can say i was *forced* by my customer to use vhdl, since
    > i largely prefers (system) verilog: half the time to do the same
    > stuff ... i tried to use vhdl in a concise manner which is competitive
    > with verlog with no success ;-)


    Using VHDL generics and entity instantiations can obviate
    configurations and component declarations in all but the most
    demanding, complex applications. These two items seem to be the most
    egregious offenders when it comes to getting real work done in vhdl
    code.

    Andy
     
    Andy, Sep 11, 2008
    #5
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Ralf Hildebrandt

    configurations and generate

    Ralf Hildebrandt, Sep 24, 2004, in forum: VHDL
    Replies:
    5
    Views:
    531
    Ralf Hildebrandt
    Oct 7, 2004
  2. Juergen Berchtel
    Replies:
    1
    Views:
    6,033
    John C. Bollinger
    May 20, 2005
  3. Matt
    Replies:
    1
    Views:
    370
    Martin Honnen
    Jul 5, 2004
  4. Chris Curvey

    shared logs and multiple configurations

    Chris Curvey, Jun 8, 2006, in forum: Python
    Replies:
    1
    Views:
    390
    Vinay Sajip
    Jun 9, 2006
  5. Soul
    Replies:
    0
    Views:
    535
Loading...

Share This Page