connect MUX to 7segment decoder???

[Rezus+]

ok i have a hw for my class and i'm really stuck on something. we have to design a 10 input mux and then a 7-segment decoder according to some tables the professor gave us. i did that correctly and now he have to connect the output of the MUX to the input of the 7segment decoder and basically connect the two .vhd files by doing the necessary changes in the code.
i tried so many things and i always get an error. i think the correct way is to use component mux and port map in the 7segment .vhd file, but i get errors.
any help greatly appreciated! thank you

these are the two files i have and the professor told me that they are correct.

Code:

-------------------------------------------------
--10 input MUX
-------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------

entity MUX is
port(
I9: in std_logic_vector(3 downto 0);
I8: in std_logic_vector(3 downto 0);
I7: in std_logic_vector(3 downto 0);
I6: in std_logic_vector(3 downto 0);
I5: in std_logic_vector(3 downto 0);
I4: in std_logic_vector(3 downto 0);
I3: in std_logic_vector(3 downto 0);
I2: in std_logic_vector(3 downto 0);
I1: in std_logic_vector(3 downto 0);
I0: in std_logic_vector(3 downto 0);
S: in std_logic_vector(9 downto 0);
O: out std_logic_vector(3 downto 0)
);
end MUX;

-------------------------------------------------

architecture behv1 of MUX is
begin
process(I9,I8,I7,I6,I5,I4,I3,I2,I1,I0,S)
begin

-- use case statement
case S is
when "1000000000" => O <= I0;
when "0100000000" => O <= I1;
when "0010000000" => O <= I2;
when "0001000000" => O <= I3;
when "0000100000" => O <= I4;
when "0000010000" => O <= I5;
when "0000001000" => O <= I6;
when "0000000100" => O <= I7;
when "0000000010" => O <= I8;
when "0000000001" => O <= I9;
when others => O <= "ZZZZ";
end case;

end process;
end behv1;

--------------------------------------------------



Code:

--============================================================================
-- BCD to 7-Segment Decoder
--============================================================================
library ieee;
use ieee.std_logic_1164.all;

entity bcd7segm is

Port (input : in std_logic_vector(3 downto 0);
a,b,c,d,e,f,g : out std_logic);
end bcd7segm;

architecture behv of bcd7segm is

Signal Segmenter: std_logic_vector(1 to 7);

begin

with input select
Segmenter <= b"1111110" when b"0000",
b"0110000" when b"0001",
b"1101101" when b"0010",
b"1111001" when b"0011",
b"0110011" when b"0100",
b"1011011" when b"0101",
b"1011111" when b"0110",
b"1110000" when b"0111",
b"1111111" when b"1000",
b"1111011" when b"1001",
b"1110111" when b"1010",
b"0011111" when b"1011",
b"1001110" when b"1100",
b"0111101" when b"1101",
b"1001111" when b"1110",
b"1000111" when b"1111",
b"0000000" when others ;

a <= Segmenter(1);
b <= Segmenter(2);
c <= Segmenter(3);
d <= Segmenter(4);
e <= Segmenter(5);
f <= Segmenter(6);
g <= Segmenter(7);

end behv;

 

[Rezus+]

anyone please?