Connecting std_logic to std_logic_vector in component declaration

Discussion in 'VHDL' started by Chris Jones, Jan 29, 2004.

  1. Chris Jones

    Chris Jones Guest

    Hello,

    I am using the System Generator tool from Xilinx to generate VHDL code
    for a DSP design. The Sys Gen tool creates components that have all
    signals defined as std_logic_vector even if they are a single bit, (0
    downto 0).

    At the next higher level, I had to create a bunch of dummy std_logic
    vector signals that is assigned from a std_logic and then I use the
    dummy signal in the component definition.

    I did this to clear up errors pertaining to mixing types.

    See code below ...


    Is there a cleaner way to solve this problem?

    Thanks,

    Chris Jones
    Engenium Technologies



    ----------------------------------------------

    U3_MODEM: flex_modem
    port map (
    adc => ADC,
    addrbus => Address,
    ctrlregdataout => CtrlRegDataOut,
    ctrlregen => CtrlRegEn_slv,
    datain => DataIn,
    dspwrite => WrPulse_slv,
    profileen => ProfileEn_slv,
    profiledataout => ProfileDataOut,
    reqdataword => ReqDataWord_slv,
    reset => (others => '0'),
    rxdataout => RxDataOut,
    rxgainhi => open,
    txrxen => TxRxEn_slv);


    -- Convert signals to standard_logic_vector in order
    -- to connect to component
    WrPulse_slv(0) <= WrPulse;
    CtrlRegEn_slv(0) <= CtrlRegEn;
    TxRxEn_slv(0) <= TxRxEn;
    ProfileEn_slv(0) <= ProfileEn;
    Chris Jones, Jan 29, 2004
    #1
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  2. "Chris Jones" <> wrote in
    message news:...

    > I am using the System Generator tool from Xilinx to generate VHDL code
    > for a DSP design. The Sys Gen tool creates components that have all
    > signals defined as std_logic_vector even if they are a single bit, (0
    > downto 0).
    >
    > At the next higher level, I had to create a bunch of dummy std_logic
    > vector signals that is assigned from a std_logic and then I use the
    > dummy signal in the component definition.

    [...]
    >
    > Is there a cleaner way to solve this problem?


    Yes; use polymorphic conversion functions on the port map.

    -- input conversion ---------------------------------------

    function vectorize(s: std_logic) return std_logic_vector is
    variable v: std_logic_vector(0 downto 0);
    begin
    v(0) := s;
    return v;
    end;

    function vectorize(v: std_logic_vector) return std_logic_vector is
    begin
    return v;
    end;

    ----Output conversion ---------------------------------------

    .... can be very similar ...

    function scalarize(v: in std_logic_vector) return std_ulogic is
    begin
    assert v'length = 1
    report "scalarize: output port must be single bit!"
    severity FAILURE;
    return v(v'LEFT);
    end;

    -------------------------------------------------------------

    OK, armed with these functions (in a package, I hope) you
    can connect up either a std_logic or a std_logic_vector
    to any suitable 1-bit vector port:

    component blah
    port (
    a: in std_logic_vector(0 downto 0);
    b: in std_logic_vector(0 downto 0);
    c: out std_logic_vector(0 downto 0)
    );
    end component;

    .....

    signal s1, s2: std_logic;
    signal v: std_logic_vector(0 downto 0);
    --instantiation...
    I1: blah port map (
    a => vectorize(s1),
    b => vectorize(v),
    scalarize(c) => s2);

    The conversion vectorize(v) is, of course, quite unnecessary;
    but it has a certain symmetrical appeal, don't you think?

    Cooler yet, you could make the component have ports to suit
    your testbench, leave the entity with its silly one-bit
    vector ports, and build a port map with conversion
    functions in a configuration.

    There's a really nice description of port-map conversion
    functions in Ben Cohen's "VHDL Answers to Frequently
    Asked Questions".
    --

    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Jan 29, 2004
    #2
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  3. Chris Jones

    Jim Lewis Guest

    You should also be able to index array ports in
    the association:

    signal s1, s2: std_logic;
    signal v: std_logic_vector(0 downto 0);

    --instantiation...
    I1: blah port map (
    a(a'left) => s1,
    b => v,
    c(c'left) => s2);


    Cheers,
    Jim

    An additional comment follows below.
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


    Jonathan Bromley wrote:


    > Cooler yet, you could make the component have ports to suit
    > your testbench, leave the entity with its silly one-bit
    > vector ports, and build a port map with conversion
    > functions in a configuration.


    Or of course you could also do bit association in the port
    map in the configuration. This one is a little closer to
    my heart as we did this after picking an ASIC vendor when
    we were well into a project and learned that the ASIC
    vendor required bit ports on the top level of the ASIC.
    So rather than switching the ports of our design to bit
    ports, we let the synthesis tool do this and fixed the
    port mapping in the configuration that ran the gate
    simulations.

    However, in hind site, it would have been easier to
    change the design source to bit ports rather than fussing
    with the configurations. We also used configurations for
    selecting test cases and mapping generics. The additional
    requirement of either mapping the gate design with bit
    ports or the original design with array ports ended up
    doubling the number of configurations we had.


    > There's a really nice description of port-map conversion
    > functions in Ben Cohen's "VHDL Answers to Frequently
    > Asked Questions".
    > --
    >
    > Jonathan Bromley, Consultant
    >
    > DOULOS - Developing Design Know-how
    > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
    >
    > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
    > Tel: +44 (0)1425 471223 mail:
    > Fax: +44 (0)1425 471573 Web: http://www.doulos.com
    >
    > The contents of this message may contain personal views which
    > are not the views of Doulos Ltd., unless specifically stated.
    >
    >
    >
    Jim Lewis, Jan 29, 2004
    #3
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