Constant and signal problem in VHDL

[Ved]

Hi Everyone,
The problem is that code is running fine till I take "IndexMx" as
CONSTANT. As soon as I change IndexMx to SIGNAL for real time
simulation, I get the "IndexMx" fine but I get the "controlsig"
as all '1's ( It should come ( 0,0,0,0,0,1,0,1,1,0,0,0,0,0,0,1).

I have been banging my head on this code since 2 days but could not
fine any mistake ! Please point out the mistake.

I need to do the following :--

I have to pick each column from matrix "IndexMx",
See if there are non-8 values in the column.
If there is a single non-8 value in the column than take that value in
WordIndex(i), and make the control flag [controlsig(i)] 'low' .
If there are more than one non-8 values than, make the control flag
[controlsig(i)] 'high'.





---Data types used:
type countArray is array (0 to N-1) of integer range -8 to 8 ;
type MATRIX_ROW is array (0 to N-1) of std_logic;
type MatrixInt is array (0 to 7 , 0 to 15) of integer range 0 to M;


entity MetricCaseSelect is
port(
clock,Reset: in std_logic;
IndexMx : in MatrixInt;
WordIndexCase: out countArray;
control : out MATRIX_ROW
);
end MetricCaseSelect;



architecture archMetricCaseSelect of MetricCaseSelect is

signal WordIndex : countArray;
signal controlsig : MATRIX_ROW;

-----signal IndexMxIN : MatrixInt;
constant IndexMx : MatrixInt := (
(8,8,8,0,8,0,8,0,0,8,8,8,8,8,8,8),
(8,8,8,8,8,1,8,1,8,8,8,8,8,1,8,1),
(8,8,8,8,8,8,8,2,2,8,8,2,8,8,8,2),
(8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8),
(8,8,8,8,4,4,8,8,4,8,8,8,8,8,8,4),
(8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8),
(8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8),
(8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8)
);
Begin

caseSelect0: process(clock,reset,count2nIN)

variable i,k: integer range 0 to 8 ;
variable j : integer range -8 to 8 ;
variable z : integer range 0 to 2 ;
variable sig : std_logic ;

begin

if reset = '1' then
sig := '0';
i := 0 ;
j := 0;
controlsig(0)<= '0';


elsif (clock'event and clock = '1') then

if ( IndexMx(i,0) /= 8 ) then

z := z + 1 ;

j := IndexMx(i,0) ;


else

end if ;

i := i + 1 ;

if (i = 8 ) then

i := 0 ;
end if ;

if (z = 2) then --As soon as I get a second non-eight
value in column, Sig is 'set'
sig := '1' ; -- If you don't want value to latch
than uncomment
-- the else part.
z := 0 ;

--else
--sig := '0' ;

end if ;

WordIndex(0) <= j ;

controlsig(0) <= sig ;

end if ;

end process caseSelect0;
.......
.......
.......
.......
.......
..---Like this I have 16 concurrent processes for every column.
.......
.......
..--------- 15th process------------------------------------
caseSelect15: process(clock,reset,count2nIN)

variable i,k: integer range 0 to 8 ;
variable j : integer range -8 to 8 ;
variable z : integer range 0 to 2 ;
variable sig : std_logic ;

begin
if reset = '1' then
sig := '0';
i := 0 ;
j := 0;
controlsig(0)<= '0';
elsif (clock'event and clock = '1') then
if ( IndexMx(i,15) /= 8 ) then
z := z + 1 ;
j := IndexMx(i,0) ;
else

end if ;
i := i + 1 ;
if (i = 8 ) then
i := 0 ;
end if ;

if (z = 2) then
sig := '1' ;
z := 0 ;
--else
--sig := '0' ;
end if ;

WordIndex(15) <= j ;
controlsig(15) <= sig ;

end if ;

end process caseSelect15;

 

[Mike Treseler]

Hi Everyone,
The problem is that code is running fine till I take "IndexMx" as
CONSTANT. As soon as I change IndexMx to SIGNAL for real time

IndexMx is the identifier for your input port and cannot be reused.
I would use IndexMx_v for the variable and IndexMx_c for the constant.

-- Mike Treseler

 

[Nicolas Matringe]

Ved a écrit :

Hi Everyone,
The problem is that code is running fine till I take "IndexMx" as
CONSTANT. As soon as I change IndexMx to SIGNAL for real time
simulation, I get the "IndexMx" fine but I get the "controlsig"
as all '1's ( It should come ( 0,0,0,0,0,1,0,1,1,0,0,0,0,0,0,1).

Hi
Your sig variable is never reset during normal operation. Once set it
will remain high until next global reset. This is why controlsig is
always all '1'.

Beware that you seem to reset controlsig(0) only, but you do it in every
process.
You should use a for ... generate loop instead of 16 identical processes.

Nicolas

 

[Ved]

Thanks for the replies

Ved a écrit :

Hi
Your sig variable is never reset during normal operation. Once set it
will remain high until next global reset. This is why controlsig is
always all '1'.

Beware that you seem to reset controlsig(0) only, but you do it in every
process.
You should use a for ... generate loop instead of 16 identical processes.

Nicolas