Constrained-random verification.

Discussion in 'VHDL' started by Slawek Grabowski, Oct 25, 2006.

  1. Hello,
    I am not familiar with the latest revisions of VHDL standard but I am
    interested in
    constrained-random verification capabilities available in VHDL.
    Does VHDL200x support constrained-random verification?
    Is it possible to generate data structures like records with constrained
    random values ?
    Otherwise, SpecMan e or SystemVerilog must be used to implement such kind of
    testbenches?

    Best Regards,
    Slawek Grabowski
     
    Slawek Grabowski, Oct 25, 2006
    #1
    1. Advertising

  2. Slawek Grabowski

    Hans Guest

    "Slawek Grabowski" <> wrote in message
    news:ehnf56$q0h$...
    > Hello,
    > I am not familiar with the latest revisions of VHDL standard but I am
    > interested in
    > constrained-random verification capabilities available in VHDL.
    > Does VHDL200x support constrained-random verification?


    It is not build into the language as is the case with SystemVerilog/SystemC
    but you can create your own CR data generators and feed that into a record.
    It is just a bit of extra work and won't be as flexible as say SystemC but
    should be doable. If you go down this route then make sure you understand
    functional verification, i.e. you need something (assert, OVL, PSL etc) to
    detect that your system is responding OK to your random stimuli unless you
    enjoy staring at lots of waveforms :)

    Hans
    www.ht-lab.com



    > Is it possible to generate data structures like records with constrained
    > random values ?
    > Otherwise, SpecMan e or SystemVerilog must be used to implement such kind
    > of testbenches?
    >
    > Best Regards,
    > Slawek Grabowski
    >
     
    Hans, Oct 25, 2006
    #2
    1. Advertising

  3. Thanks Hans, I have started with SystemC and probably use some assertions.
    BTW: SystemC appears to be really slow.
    IEEE mentions somewhere in the internet that constrained random verification
    will be
    added to VHDL in 2007.

    Best Regards,
    Slawek Grabowski



    "Hans" <> wrote in message
    news:1EM%g.27937$...
    >
    > "Slawek Grabowski" <> wrote in message
    > news:ehnf56$q0h$...
    >> Hello,
    >> I am not familiar with the latest revisions of VHDL standard but I am
    >> interested in
    >> constrained-random verification capabilities available in VHDL.
    >> Does VHDL200x support constrained-random verification?

    >
    > It is not build into the language as is the case with
    > SystemVerilog/SystemC but you can create your own CR data generators and
    > feed that into a record. It is just a bit of extra work and won't be as
    > flexible as say SystemC but should be doable. If you go down this route
    > then make sure you understand functional verification, i.e. you need
    > something (assert, OVL, PSL etc) to detect that your system is responding
    > OK to your random stimuli unless you enjoy staring at lots of waveforms
    > :)
    >
    > Hans
    > www.ht-lab.com
    >
    >
    >
    >> Is it possible to generate data structures like records with constrained
    >> random values ?
    >> Otherwise, SpecMan e or SystemVerilog must be used to implement such kind
    >> of testbenches?
    >>
    >> Best Regards,
    >> Slawek Grabowski
    >>

    >
    >
     
    Slawek Grabowski, Oct 26, 2006
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. cltsaig

    Port "arg" is not constrained?

    cltsaig, Oct 12, 2004, in forum: VHDL
    Replies:
    2
    Views:
    748
    cltsaig
    Oct 12, 2004
  2. globalrev
    Replies:
    4
    Views:
    818
    Gabriel Genellina
    Apr 20, 2008
  3. JimLewis
    Replies:
    3
    Views:
    1,300
    JimLewis
    Apr 13, 2009
  4. VK
    Replies:
    15
    Views:
    1,332
    Dr J R Stockton
    May 2, 2010
  5. alb
    Replies:
    1
    Views:
    268
    Jim Lewis
    Dec 6, 2013
Loading...

Share This Page