constraints, etc

Discussion in 'VHDL' started by Jason Berringer, Jul 4, 2003.

  1. Hello all,

    I would like to know a couple of things if anyone could help or point me to
    a file etc. I'm using Webpack from Xilinx, and a Spartan XC2S100 and I've
    been messing around with writing simple project to get familiar with VHDL
    and programming the board. I'm curious to know if I have to instantiate a
    global clock buffer each time I sythesis my design, or if I simply make sure
    that my clock goes to a GCK pin is that enough? Also I'm a little confused
    as to what constraints are and how they might help my designs. For example
    if I have a 30 MHz clock going to a GCK pin do I have to put constraints on
    it or are constraints primarily used for very complex designs?

    Sorry if this seems like small question, but it is somewhat confusing from
    the documents that I have read, and since I haven't had any problems with
    any of my projects (without using any constraints) I was not all that
    worried. Now that I'm getting into bigger designs I figured that it was time
    to start figuring this out.

    Any and all help is greatly appreciated.

    Thanks

    Jason
    Jason Berringer, Jul 4, 2003
    #1
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