constuire un bus 64bits avec des data 8bits

Discussion in 'VHDL' started by picnanard, Mar 15, 2007.

  1. picnanard

    picnanard

    Joined:
    Mar 5, 2007
    Messages:
    19
    salut a tous,

    Comment peut on construire un std_logic_vector(63 downto 0)
    a partir de 8 std_logic_vector(7downto 0)
    donc comment constuire une data 64bits avec 8 data de 8bits
    en vhdl.:flute:

    merci de votre aide
     
    picnanard, Mar 15, 2007
    #1
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