Content of RAM in Modelsim

Discussion in 'VHDL' started by ALuPin, Sep 29, 2004.

  1. ALuPin

    ALuPin Guest

    Hi,

    I use the ALTSYNCRAM component in Altera QuartusII version 4.1 SP2

    It has the following ports:

    data_a[35..0]
    address_a[1..0]
    wren_a
    byteena_a[3..0]
    q_a[35..0]
    clock_a
    aclr_a

    data_b[35..0]
    address_b[1..0]
    wren_b
    q_b[35..0]
    clock_b
    aclr_b

    To make the content of the RAM visible during simulation with MODELSIM
    I choose the component ALTSYNCRAM in Modelsim and open the PROCESS
    and the VARIABLES window.
    When I choose the line__21837 I see the variable m_mem_data_a which
    seems to represent the content of the RAM.

    When I add this array to my wave window and simulate my design I can see
    that m_mem_data_a changes while 'wren_b' is high ? ('wren_a' is deasserted)
    The output a PORT A q_a also changes its value.

    I do not understand that. Why does the output of PORT A change with
    the clock of PORT B when 'wren_b' is asserted?

    Does m_mem_data_a show the content with reference to PORT A or PORT B or
    both?

    When I look at an additional array called "m_mem_data_b" I see that
    its content remains "XXX...XXX" during the complete simulation. So what
    does this array represent?


    Any idea of what is going on ?

    I would appreciate your help.

    Rgds
    ALuPin, Sep 29, 2004
    #1
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