Control Register implementation

Discussion in 'VHDL' started by gommo, Oct 28, 2004.

  1. gommo

    gommo Guest

    I have a 8bit control register that in a PLD that resides at 0x330 on
    an ISA bus.

    I want to be able to have some bits in the control register read-only,
    read/write, and write-only.

    I have something like this

    process (IOR)
    begin
    if (Falling_edge(IOR) and CRS = '0') then
    -- Place the Control register onto the databus but ensure
    the write-only
    -- Data is correct
    SD <= (reg and "11111110");
    end if;
    end process;

    process (IOW)
    begin
    if (Falling_edge(IOW) and CRS = '0') then
    -- Read the data from the databus but don't write over the read-only
    bits
    reg(4) <= SD(4);
    reg(3) <= SD(3);
    reg(2) <= SD(2);
    reg(1) <= SD(1);
    reg(0) <= SD(0);
    end if;
    end process;

    However, doing it this way means that if I write data to the Data-bus I
    need to tri-state the databus somehow? How can I do this/ when and
    where???

    Thanks
     
    gommo, Oct 28, 2004
    #1
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  2. gommo

    rickman Guest

    gommo wrote:
    >
    > I have a 8bit control register that in a PLD that resides at 0x330 on
    > an ISA bus.
    >
    > I want to be able to have some bits in the control register read-only,
    > read/write, and write-only.
    >
    > I have something like this
    >
    > process (IOR)
    > begin
    > if (Falling_edge(IOR) and CRS = '0') then
    > -- Place the Control register onto the databus but ensure
    > the write-only
    > -- Data is correct
    > SD <= (reg and "11111110");
    > end if;
    > end process;
    >
    > process (IOW)
    > begin
    > if (Falling_edge(IOW) and CRS = '0') then
    > -- Read the data from the databus but don't write over the read-only
    > bits
    > reg(4) <= SD(4);
    > reg(3) <= SD(3);
    > reg(2) <= SD(2);
    > reg(1) <= SD(1);
    > reg(0) <= SD(0);
    > end if;
    > end process;
    >
    > However, doing it this way means that if I write data to the Data-bus I
    > need to tri-state the databus somehow? How can I do this/ when and
    > where???


    This is another example of how trying to write HDL code is not a good
    way to design hardware. First picture the hardware you want to
    describe. Then describe it with the language. You have made at least
    two major mistakes that I have spotted quickly. You have an idea about
    the problem with the tristate. You need to have three busses, an IO bus
    with is the actual pins of the device. This is connected to an input
    bus by a simple assignment and an output bus by a tristate conditional.

    -- IOR is low true?
    SD <= (others => 'Z') when (CSR = '0' and IOR = '0') else outdata;

    outdata is assigned from the bits you want to be able to read. You
    don't need to and, just pick off the bits you want. And don't put this
    in a clocked process. The conditional above will handle the gating.

    outdata <= reg(7 downto 1) & '0'

    indata is used in the clocked process to set reg. If IOW is low true,
    the rising edge is typically used to clock the data since that gives the
    most setup time, but I don't know your timing issues.

    reg(4 downto 0) <= SD (4 downto 0);

    --

    Rick "rickman" Collins


    Ignore the reply address. To email me use the above address with the XY
    removed.

    Arius - A Signal Processing Solutions Company
    Specializing in DSP and FPGA design URL http://www.arius.com
    4 King Ave 301-682-7772 Voice
    Frederick, MD 21701-3110 301-682-7666 FAX
     
    rickman, Oct 28, 2004
    #2
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